//hyperion register definition for fpga registeroffset A32
	{ ebrhDMACtrlNII51006,	A32_NII51006, 1 },
	{ ebrhSystemRegister,	A32_SYSTEM_REGISTER, 1 },
	{ ebrhI2CRead,			A32_IIC_READ, 1 },
	{ ebrhAsmiInterface,	A32_ASMI_INTERFACE, 1 },
	{ ebrhDMACtrlVideoIn0,	A32_VIDEO_IN_DMA_0, 1 },
	{ ebrhDMACtrlVideoIn1,	A32_VIDEO_IN_DMA_1, 1 },
	{ ebrhDMACtrlPCI0,		A32_DDR_PCI_DMA_0, 1 },
	{ ebrhDMACtrlPCI1,		A32_DDR_PCI_DMA_0, 1 },
	{ ebrhPoCLCtrl0,		A32_POCL_CONTROL_0, 1 },
	{ ebrhPoCLCtrl1,		A32_POCL_CONTROL_1, 1 },
	{ ebrhUart0,			A32_UART_0, 1 },
	{ ebrhUart1,			A32_UART_1, 1 },
	{ ebrhCLController0,	A32_CL_CONTROLLER_0, 1 },
	{ ebrhCLController1,	A32_CL_CONTROLLER_1, 1 },
	{ ebrhHrtController0,	A32_HRT_CONTROLLER_0, 1 },
	{ ebrhHrtController1,	A32_HRT_CONTROLLER_1, 1 },
	{ ebrhPCICore,			PCI_CORE_REGISTER, 1 },
	{ ebrhTriggerHrtController0,	A32_TRIGGER_HRT_CONTROLLER_0, 1 },
	{ ebrhTriggerHrtController1,	A32_TRIGGER_HRT_CONTROLLER_1, 1 },
	{ ebrhOnChipMemData,	0, 1 }
