//hyperion register definition for fpga registeroffset cl4e
	{ ebrhDMACtrlNII51006,	CL4E_NII51006, 2 },
	{ ebrhSystemRegister,	CL4E_SYSTEM_REGISTER, 2 },
	{ ebrhI2CRead,			CL4E_IIC_READ, 2 },
	{ ebrhAsmiInterface,	CL4E_ASMI_INTERFACE, 1 },
	{ ebrhDMACtrlVideoIn0,	CL4E_VIDEO_IN_DMA_0, 2 },
	{ ebrhDMACtrlVideoIn1,	CL4E_VIDEO_IN_DMA_1, 2 },
	{ ebrhDMACtrlPCI0,		CL4E_DDR_PCI_DMA_0, 2 },
	{ ebrhDMACtrlPCI1,		CL4E_DDR_PCI_DMA_0, 2 },
	{ ebrhPoCLCtrl0,		CL4E_POCL_CONTROL_0, 2 },
	{ ebrhPoCLCtrl1,		CL4E_POCL_CONTROL_1, 2 },
	{ ebrhUart0,			CL4E_UART_0, 2 },
	{ ebrhUart1,			CL4E_UART_1, 2 },
	{ ebrhCLController0,	CL4E_CL_CONTROLLER_0, 2 },
	{ ebrhCLController1,	CL4E_CL_CONTROLLER_1, 2 },
	{ ebrhHrtController0,	CL4E_HRT_CONTROLLER_0, 2 },
	{ ebrhHrtController1,	CL4E_HRT_CONTROLLER_1, 2 },
	{ ebrhPCICore,			PCI_EXPRESS_CORE_REGISTER, 1 },
	{ ebrhTriggerHrtController0,	CL4E_TRIGGER_HRT_CONTROLLER_0, 2 },
	{ ebrhTriggerHrtController1,	CL4E_TRIGGER_HRT_CONTROLLER_1, 2 },
	{ ebrhOnChipMemData,	0, 1 }
