//hyperion register definition for fpga registeroffset cl4e
	{ ebrhDMACtrlNII51006,	0, 2 },
	{ ebrhSystemRegister,	HDSDI_4E_SYSTEM_REGISTER, 2 },
	{ ebrhI2CRead,			HDSDI_4E_IIC_READ, 2 },
	{ ebrhAsmiInterface,	HDSDI_4E_EPCS_CONTROLLER, 1 },
	{ ebrhDMACtrlVideoIn0,	HDSDI_4E_VIDEO_IN_DMA_0, 2 },
	{ ebrhDMACtrlVideoIn1,	HDSDI_4E_VIDEO_IN_DMA_1, 2 },
	{ ebrhDMACtrlPCI0,		0, 2 },
	{ ebrhDMACtrlPCI1,		0, 2 },
	{ ebrhPoCLCtrl0,		0, 2 },
	{ ebrhPoCLCtrl1,		0, 2 },
	{ ebrhUart0,			HDSDI_4E_NICE_UART, 2 },
	{ ebrhUart1,			HDSDI_4E_NICE_UART, 2 },
	{ ebrhCLController0,	HDSDI_4E_CL_CONTROLLER_0, 2 },
	{ ebrhCLController1,	HDSDI_4E_CL_CONTROLLER_1, 2 },
	{ ebrhHrtController0,	HDSDI_4E_HRT_CONTROLLER_0, 2 },
	{ ebrhHrtController1,	HDSDI_4E_HRT_CONTROLLER_1, 2 },
	{ ebrhPCICore,			PCI_EXPRESS_CORE_REGISTER, 1 },
	{ ebrhTriggerHrtController0,	HDSDI_4E_TRIGGER_HRT_CONTROLLER_0, 2 },
	{ ebrhTriggerHrtController1,	HDSDI_4E_TRIGGER_HRT_CONTROLLER_1, 2 },
	{ ebrhOnChipMemData,	0, 1 },
	{ ebrhSPISimple,		HDSDI_4E_SPI_SIMPLE, 2 },
	{ ebrhDecCtrl0,			HDSDI_4E_DEC_CTRL_0, 2 },
	{ ebrhDecCtrl1,			HDSDI_4E_DEC_CTRL_1, 2 }

