00001 /** ============================================================================ 00002 * @file linkcfgdefs.h 00003 * 00004 * @path $(DSPLINK)/gpp/inc/usr/ 00005 * 00006 * @brief Defines constants and interfaces for configuration of DSPLINK. 00007 * 00008 * @ver 1.65.00.03 00009 * ============================================================================ 00010 * @copyright Copyright (C) 2002-2009, Texas Instruments Incorporated - 00011 * http://www.ti.com/ 00012 * 00013 * Redistribution and use in source and binary forms, with or without 00014 * modification, are permitted provided that the following conditions 00015 * are met: 00016 * 00017 * * Redistributions of source code must retain the above copyright 00018 * notice, this list of conditions and the following disclaimer. 00019 * 00020 * * Redistributions in binary form must reproduce the above copyright 00021 * notice, this list of conditions and the following disclaimer in the 00022 * documentation and/or other materials provided with the distribution. 00023 * 00024 * * Neither the name of Texas Instruments Incorporated nor the names of 00025 * its contributors may be used to endorse or promote products derived 00026 * from this software without specific prior written permission. 00027 * 00028 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00029 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 00030 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 00031 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 00032 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 00033 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 00034 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 00035 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 00036 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 00037 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 00038 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00039 * ============================================================================ 00040 */ 00041 00042 00043 #if !defined (LINKCFGDEFS_H) 00044 #define LINKCFGDEFS_H 00045 00046 00047 /* ----------------------------------- DSP/BIOS LINK Headers */ 00048 #include <dsplink.h> 00049 #include <linkcfgdefs_os.h> 00050 00051 00052 #if defined (__cplusplus) 00053 EXTERN "C" { 00054 #endif /* defined (__cplusplus) */ 00055 00056 00057 /** ============================================================================ 00058 * @name LINKCFG_Gpp 00059 * 00060 * @brief This structure defines the configuration structure for the GPP. 00061 * 00062 * @param name 00063 * Name of GPP Processor. 00064 * @param maxMsgqs 00065 * Maximum MSGQs that can be opened on the GPP. 00066 * @param maxChnlQueue 00067 * Maximum Queue Length for all channels created on the GPP. 00068 * @param poolTableId 00069 * POOL table ID to be used for intra-GPP communication. A value of 00070 * -1 indicates that no POOL is required by the GPP. 00071 * @param numPools 00072 * Number of POOLs within the pool table for the GPP. 00073 * @param gppOsObject 00074 * Pointer to the GPP OS-specific configuration object. 00075 * ============================================================================ 00076 */ 00077 typedef struct LINKCFG_Gpp_tag { 00078 Char8 name [DSP_MAX_STRLEN] ; 00079 Uint32 maxMsgqs ; 00080 Uint32 maxChnlQueue ; 00081 Uint32 poolTableId ; 00082 Uint32 numPools ; 00083 LINKCFG_GppOs * gppOsObject ; 00084 } LINKCFG_Gpp ; 00085 00086 00087 /** ============================================================================ 00088 * @name DSP_BootMode 00089 * 00090 * @brief This structure defines the configuration structure for the GPP. 00091 * 00092 * @param DSP_BootMode_Boot_NoPwr 00093 * This is backward compatible with the default false i.e. 00094 * DSPLINK_BOOT_MODE. Wherein DSPLink does not do power management 00095 * of DSP 00096 * PROC_attach will put DSP in local reset. It will not power up 00097 * the DSP. 00098 * PROC_start will set entry point for DSP i.e. c_int00 and release 00099 * DSP from reset. 00100 * PROC_stop will put DSP in local reset. 00101 * PROC_detach will not power down the DSP. 00102 * 00103 * @param DSP_BootMode_Boot_Pwr 00104 * This is backward compatible with the default true i.e. 00105 * DSPLINK_BOOT_MODE. Wherein DSPLink does power management of DSP 00106 * PROC_attach will put DSP in local reset. It will power up the 00107 * DSP. 00108 * PROC_start will set entry point for DSP i.e. c_int00 and release 00109 * DSP from reset. 00110 * PROC_stop will put DSP in local reset. 00111 * PROC_detach will power down the DSP. 00112 * 00113 * @param DSP_BootMode_NoLoad_NoPwr 00114 * This is added to support DSPLINK_NOLOAD_MODE. 00115 * PROC_attach will put DSP in local reset. It will not power up 00116 * the DSP. 00117 * PROC_start will set entry point for DSP i.e. c_int00 and release 00118 * DSP from reset 00119 * PROC_stop will put DSP in local reset. 00120 * PROC_detach will not power down the DSP. 00121 * 00122 * @param DSP_BootMode_NoLoad_Pwr 00123 * This is added to support DSPLINK_NOLOAD_MODE. 00124 * PROC_attach will put DSP in local reset. It will power up 00125 * the DSP. 00126 * PROC_start will set entry point for DSP i.e. c_int00 and release 00127 * DSP from reset 00128 * PROC_stop will put DSP in local reset. 00129 * PROC_detach will power down the DSP. 00130 * 00131 * @param DSP_BootMode_NoBoot 00132 * This is added to support DSPLINK_NOBOOT_MODE 00133 * PROC_attach will not put DSP in local reset. It will not power 00134 * up the DSP. 00135 * PROC_start will not set entry point for DSP i.e. c_int00 and 00136 * not release DSP from reset 00137 * PROC_stop will not put DSP in local reset. 00138 * PROC_detach will not power down the DSP. 00139 * 00140 * ============================================================================ 00141 */ 00142 typedef enum { 00143 DSP_BootMode_Boot_NoPwr = 0x0, 00144 DSP_BootMode_Boot_Pwr, 00145 DSP_BootMode_NoLoad_NoPwr, 00146 DSP_BootMode_NoLoad_Pwr, 00147 DSP_BootMode_NoBoot 00148 } DSP_BootMode ; 00149 00150 /** ============================================================================ 00151 * @name Endianism 00152 * 00153 * @brief Enumeration of data endianism. 00154 * 00155 * @param Endianism_Default 00156 * Default endianism - no conversion required. 00157 * @param Endianism_Big 00158 * Big endian. 00159 * @param Endianism_Little 00160 * Little endian. 00161 * ============================================================================ 00162 */ 00163 typedef enum { 00164 Endianism_Default = 1u, 00165 Endianism_Big = 2u, 00166 Endianism_Little = 3u 00167 } Endianism ; 00168 00169 /** ============================================================================ 00170 * @name DspArch 00171 * 00172 * @brief Enumerates the various architectures of DSP supported by 00173 * DSP/BIOS LINK. 00174 * 00175 * @param DspArch_Unknown 00176 * It indicates that the architecture is not supported. 00177 * @param DspArch_C55x 00178 * It indicates that the architecture is C55x. 00179 * @param DspArch_C64x 00180 * It indicates that the architecture is C64x. 00181 * @param DspArch_C64x_Bios5 00182 * It indicates that the architecture is C64x and the 00183 * DSP OS version is DSP/BIOS 5.xx. 00184 * @param DspArch_C64x_Bios6 00185 * It indicates that the architecture is C64x and the 00186 * DSP OS version is DSP/BIOS 6.xx. 00187 * ============================================================================ 00188 */ 00189 typedef enum { 00190 DspArch_Unknown = 0u, 00191 DspArch_C55x = 1u, 00192 DspArch_C64x = 2u, 00193 DspArch_C64x_Bios5 = 3u, 00194 DspArch_C64x_Bios6 = 4u 00195 } DspArch ; 00196 00197 /** ============================================================================ 00198 * @name LINKCFG_Dsp 00199 * 00200 * @brief This structure defines the configuration structure for the DSP. 00201 * 00202 * @param name 00203 * Name of DSP processor. 00204 * @param dspArch 00205 * Architecture of the DSP. 00206 * @param loaderName 00207 * Name of loader to be used for loading the DSP executable. 00208 * @param autoStart 00209 * AutoStart flag indicating whether a default DSP image should be 00210 * loaded on startup. 00211 * Currently not supported. 00212 * @param execName 00213 * Name of executable to load in case autostart is used. 00214 * @param doDspCtrl 00215 * Indicates whether DSP/BIOS LINK should do the dsp control for 00216 * the DSP. This depends on the DSPLink boot mode chosen. 00217 * @param resumeAddr 00218 * The resume address after hibernating. 00219 * @param resetVector 00220 * Address of reset vector of DSP. 00221 * @param resetCodeSize 00222 * Size of code at DSP Reset Vector. 00223 * @param maduSize 00224 * Minimum addressable unit on the DSP. 00225 * @param cpuFreq 00226 * The frequency at which the DSP is running (in KHz). 00227 * Specify -1 if the cpuFreq is not to be set from GPP-side and the 00228 * default DSP/BIOS setting is to be used. 00229 * @param endian 00230 * Endianism info of DSP. 00231 * @param wordSwap 00232 * Indicates whether words need to be swapped while writing into 00233 * the memory for the DSP. 00234 * @param memTableId 00235 * Table number of the MEM entries for this DSP. 00236 * @param memEntries 00237 * Number of entries in the MEM table. 00238 * @param linkDrvId 00239 * Link Driver table identifier for this DSP. 00240 * @param arg1 00241 * Platform specific argument. 00242 * @param arg2 00243 * Platform specific argument. 00244 * @param arg3 00245 * Platform specific argument. 00246 * @param arg4 00247 * Platform specific argument. 00248 * @param arg5 00249 * Platform specific argument. 00250 * ============================================================================ 00251 */ 00252 typedef struct LINKCFG_Dsp_tag { 00253 Char8 name [DSP_MAX_STRLEN] ; 00254 Uint32 dspArch ; 00255 Char8 loaderName [DSP_MAX_STRLEN] ; 00256 Bool autoStart ; 00257 Char8 execName [DSP_MAX_STRLEN] ; 00258 DSP_BootMode doDspCtrl ; 00259 Uint32 resumeAddr ; 00260 Uint32 resetVector ; 00261 Uint32 resetCodeSize ; 00262 Uint32 maduSize ; 00263 Uint32 cpuFreq ; 00264 Uint32 endian ; 00265 Uint32 wordSwap ; 00266 Uint32 memTableId ; 00267 Uint32 memEntries ; 00268 Uint32 linkDrvId ; 00269 Uint32 arg1 ; 00270 Uint32 arg2 ; 00271 Uint32 arg3 ; 00272 Uint32 arg4 ; 00273 Uint32 arg5 ; 00274 } LINKCFG_Dsp ; 00275 00276 00277 /** ============================================================================ 00278 * @name LINKCFG_MemEntry 00279 * 00280 * @brief This structure defines an entry in the MEM table. 00281 * 00282 * @param entry 00283 * Entry number in the memory table. 00284 * @param name 00285 * Name identifying the memory region. 00286 * @param physAddr 00287 * Physical address of the memory region. 00288 * @param dspVirtAddr 00289 * DSP virtual address of the memory region. 00290 * @param gppVirtAddr 00291 * GPP virtual address of the memory region. If specified as -1, 00292 * the GPP virtual address is assumed to be invalid, and shall be 00293 * set internally within the DSPLINK driver. 00294 * @param size 00295 * Size of the memory region. 00296 * @param shared 00297 * Flag indicating whether the memory region is shared between GPP 00298 * and DSP. 00299 * @param syncd 00300 * Flag indicating whether the memory region is synchonized 00301 * between GPP and DSP. 00302 * ============================================================================ 00303 */ 00304 typedef struct LINKCFG_MemEntry_tag { 00305 Uint32 entry ; 00306 Char8 name [DSP_MAX_STRLEN] ; 00307 Uint32 physAddr ; 00308 Uint32 dspVirtAddr ; 00309 Uint32 gppVirtAddr ; 00310 Uint32 size ; 00311 Bool shared ; 00312 Bool syncd ; 00313 } LINKCFG_MemEntry ; 00314 00315 00316 /** ============================================================================ 00317 * @name LINKCFG_LinkDrv 00318 * 00319 * @brief This structure defines the configuration information for the 00320 * physical link driver. 00321 * 00322 * @param name 00323 * Name of the physical link driver. 00324 * @param hshkPollCount 00325 * Poll count to be used for the handshake between GPP and DSP. The 00326 * GPP spins in a loop for number of iterations equal to the 00327 * handshake poll count or till the DSP completes its handshake. 00328 * A value of -1 indicates infinite wait. 00329 * @param memEntry 00330 * MEM Entry for the memory area used by this physical link. 00331 * This field is optional and can be specified as -1 in case 00332 * a MEM entry is not required. 00333 * @param ipsTableId 00334 * IPS table ID. 00335 * @param numIpsEntries 00336 * Number of IPS table entries for this link driver. 00337 * @param poolTableId 00338 * POOL table ID. 00339 * @param numPools 00340 * Number of POOLs within the pool table for this link driver. 00341 * @param dataTableId 00342 * Table number of the data driver(s) used with this DSP. 00343 * @param numDataDrivers 00344 * Number of data drivers used with this DSP. 00345 * @param mqtId 00346 * The ID of the MQT which is to be used for this DSP. 00347 * @param ringIoTableId 00348 * Table number of the RINGIO object(s) for this DSP. 00349 * @param mplistTableId 00350 * Table number of the MPLIST object(s) for this DSP. 00351 * @param mpcsTableId 00352 * Table number of the MPCS object(s) for this DSP. 00353 * ============================================================================ 00354 */ 00355 typedef struct CFG_LinkDrv_tag { 00356 Char8 name [DSP_MAX_STRLEN] ; 00357 Uint32 hshkPollCount ; 00358 Uint32 memEntry ; 00359 Uint32 ipsTableId ; 00360 Uint32 numIpsEntries ; 00361 Uint32 poolTableId ; 00362 Uint32 numPools ; 00363 Uint32 dataTableId ; 00364 Uint32 numDataDrivers ; 00365 Uint32 mqtId ; 00366 Uint32 ringIoTableId ; 00367 Uint32 mplistTableId ; 00368 Uint32 mpcsTableId ; 00369 } LINKCFG_LinkDrv ; 00370 00371 00372 /** ============================================================================ 00373 * @name LINKCFG_Ips 00374 * 00375 * @brief This structure defines the configuration information for the 00376 * Inter-processor Signaling Component. 00377 * 00378 * @param name 00379 * Name of the IPS component. 00380 * @param numIpsEvents 00381 * Number of events supported by the IPS. 00382 * @param memEntry 00383 * MEM entry for the memory area used for this IPS component. 00384 * This field is optional and can be specified as -1 in case 00385 * a MEM entry is not required. 00386 * @param gppIntId 00387 * Interrupt Number to used by the IPS on GPP-side. 00388 * @param dspIntId 00389 * Interrupt Number to used by the IPS on DSP-side. 00390 * @param dspIntVectorId 00391 * Interrupt Vector Number to used by the IPS on DSP-side. 00392 * @param arg1 00393 * First IPS-specific optional argument. 00394 * @param arg2 00395 * Second IPS-specific optional argument. 00396 * ============================================================================ 00397 */ 00398 typedef struct LINKCFG_Ips_tag { 00399 Char8 name [DSP_MAX_STRLEN] ; 00400 Uint32 numIpsEvents ; 00401 Uint32 memEntry ; 00402 Uint32 gppIntId ; 00403 Uint32 dspIntId ; 00404 Uint32 dspIntVectorId ; 00405 Uint32 arg1 ; 00406 Uint32 arg2 ; 00407 } LINKCFG_Ips ; 00408 00409 00410 /** ============================================================================ 00411 * @name LINKCFG_Pool 00412 * 00413 * @brief This structure defines the configuration information for a buffer 00414 * pool, from which buffers for use with DSPLINK can be allocated 00415 * through the POOL interface(s). 00416 * 00417 * @param name 00418 * Name of the pool. 00419 * @param memEntry 00420 * MEM Entry for the memory area used by this buffer pool. 00421 * This field is optional and can be specified as -1 in case 00422 * a MEM entry is not required. 00423 * @param poolSize 00424 * Size of the buffer pool. 00425 * @param ipsId 00426 * ID of the IPS used (if any). A value of -1 indicates that no IPS 00427 * is required by the pool. 00428 * @param ipsEventNo 00429 * IPS Event number associated with POOL (if any). A value of -1 00430 * indicates that no IPS is required by the pool. 00431 * @param poolMemEntry 00432 * Pool memory region section ID. 00433 * @param arg1 00434 * First optional pool-specific argument. 00435 * @param arg2 00436 * Second optional pool-specific argument. 00437 * ============================================================================ 00438 */ 00439 typedef struct LINKCFG_Pool_tag { 00440 Char8 name [DSP_MAX_STRLEN] ; 00441 Uint32 memEntry ; 00442 Uint32 poolSize ; 00443 Uint32 ipsId ; 00444 Uint32 ipsEventNo ; 00445 Uint32 poolMemEntry ; 00446 Uint32 arg1 ; 00447 Uint32 arg2 ; 00448 } LINKCFG_Pool ; 00449 00450 00451 /** ============================================================================ 00452 * @name LINKCFG_DataDrv 00453 * 00454 * @brief This structure defines the configuration structure for the data 00455 * streaming driver using the CHNL component. 00456 * 00457 * @param name 00458 * Name of the data transfer driver. 00459 * @param baseChnlId 00460 * Base channel ID for this data driver. 00461 * @param numChannels 00462 * Number of logical channels for this data driver. 00463 * @param maxBufSize 00464 * Maximum size of data buffer supported by this data driver. If 00465 * no limit is imposed by the driver, a value of -1 can be 00466 * specified. 00467 * @param memEntry 00468 * MEM entry for the memory area for data streaming driver. 00469 * This field is optional and can be specified as -1 in case 00470 * a MEM entry is not required. 00471 * @param poolId 00472 * Identifier for the pool from where buffers are allocated. 00473 * @param queuePerChnl 00474 * Buffer Queue length on each channel supported by the data 00475 * driver. 00476 * @param ipsId 00477 * ID of the IPS to be used (if any). A value of -1 indicates that 00478 * no IPS is required by the data driver. 00479 * @param ipsEventNo 00480 * IPS Event number associated with data driver (if any). A value 00481 * of -1 indicates that no IPS is required by the data driver. 00482 * @param arg1 00483 * First optional data driver specific argument. 00484 * The significance of this argument is specific to a data driver. 00485 * @param arg2 00486 * Second optional data driver specific argument 2. 00487 * The significance of this argument is specific to a data driver. 00488 * ============================================================================ 00489 */ 00490 typedef struct LINKCFG_DataDrv_tag { 00491 Char8 name [DSP_MAX_STRLEN] ; 00492 Uint32 baseChnlId ; 00493 Uint32 numChannels ; 00494 Uint32 maxBufSize ; 00495 Uint32 memEntry ; 00496 Uint32 poolId ; 00497 Uint32 queuePerChnl ; 00498 Uint32 ipsId ; 00499 Uint32 ipsEventNo ; 00500 Uint32 arg1 ; 00501 Uint32 arg2 ; 00502 } LINKCFG_DataDrv ; 00503 00504 00505 /** ============================================================================ 00506 * @name LINKCFG_Mqt 00507 * 00508 * @brief This structure defines the configuration structure for the Message 00509 * Queue Transport. 00510 * 00511 * @param name 00512 * Name of the MQT. 00513 * @param memEntry 00514 * MEM entry id for the memory area used by this MQT. 00515 * This field is optional and can be specified as -1 in case 00516 * a MEM entry is not required. 00517 * @param maxMsgSize 00518 * Maximum size of message supported by MQT. May be -1 if there is 00519 * no limit on maximum message size for the MQT. 00520 * @param ipsId 00521 * ID of the IPS to be used (if any). A value of -1 indicates that 00522 * no IPS is required by the MQT. 00523 * @param ipsEventNo 00524 * IPS Event number associated with MQT (if any). A value of -1 00525 * indicates that no IPS is required by the MQT. 00526 * @param arg1 00527 * First optional argument for this MQT. 00528 * The significance of this argument is specific to the MQT. 00529 * @param arg2 00530 * Second optional argument for this MQT. 00531 * The significance of this argument is specific to the MQT. 00532 * ============================================================================ 00533 */ 00534 typedef struct LINKCFG_Mqt_tag { 00535 Char8 name [DSP_MAX_STRLEN] ; 00536 Uint32 memEntry ; 00537 Uint32 maxMsgSize ; 00538 Uint32 ipsId ; 00539 Uint32 ipsEventNo ; 00540 Uint32 arg1 ; 00541 Uint32 arg2 ; 00542 } LINKCFG_Mqt ; 00543 00544 00545 /** ============================================================================ 00546 * @name LINKCFG_RingIo 00547 * 00548 * @brief This structure defines the configuration structure for the RingIO 00549 * component. 00550 * 00551 * @param name 00552 * Name of the RingIO. 00553 * @param memEntry 00554 * MEM entry ID for the memory area used by this RingIO. 00555 * @param maxEntries 00556 * Maximum number of RingIO instances supported by the RingIO. 00557 * @param ipsId 00558 * ID of the IPS to be used. 00559 * @param ipsEventNo 00560 * IPS Event number associated with the RingIO. 00561 * ============================================================================ 00562 */ 00563 typedef struct LINKCFG_RingIo_tag { 00564 Char8 name [DSP_MAX_STRLEN] ; 00565 Uint32 memEntry ; 00566 Uint32 maxEntries ; 00567 Uint32 ipsId ; 00568 Uint32 ipsEventNo ; 00569 } LINKCFG_RingIo ; 00570 00571 00572 /** ============================================================================ 00573 * @name LINKCFG_MpList 00574 * 00575 * @brief This structure defines the configuration structure for the MPLIST 00576 * component. 00577 * 00578 * @param name 00579 * Name of the MPLIST. 00580 * @param memEntry 00581 * MEM entry ID for the memory area used by this MPLIST. 00582 * @param maxEntries 00583 * Maximum number of MPLIST instances supported by the MPLIST. 00584 * @param ipsId 00585 * ID of the IPS to be used (if any). A value of -1 indicates that 00586 * no IPS is required by the MPLIST. 00587 * @param ipsEventNo 00588 * IPS Event number associated with MPLIST (if any). A value of -1 00589 * indicates that no IPS is required by the MPLIST. 00590 * ============================================================================ 00591 */ 00592 typedef struct LINKCFG_MpList_tag { 00593 Char8 name [DSP_MAX_STRLEN] ; 00594 Uint32 memEntry ; 00595 Uint32 maxEntries ; 00596 Uint32 ipsId ; 00597 Uint32 ipsEventNo ; 00598 } LINKCFG_MpList ; 00599 00600 00601 /** ============================================================================ 00602 * @name LINKCFG_Mpcs 00603 * 00604 * @brief This structure defines the configuration structure for the MPCS 00605 * component. 00606 * 00607 * @param name 00608 * Name of the MPCS. 00609 * @param memEntry 00610 * MEM entry ID for the memory area used by this MPCS. 00611 * @param maxEntries 00612 * Maximum number of MPCS instances supported by the MPCS. 00613 * @param ipsId 00614 * ID of the IPS to be used (if any). A value of -1 indicates that 00615 * no IPS is required by the MPCS. 00616 * @param ipsEventNo 00617 * IPS Event number associated with MPCS (if any). A value of -1 00618 * indicates that no IPS is required by the MPCS. 00619 * ============================================================================ 00620 */ 00621 typedef struct LINKCFG_Mpcs_tag { 00622 Char8 name [DSP_MAX_STRLEN] ; 00623 Uint32 memEntry ; 00624 Uint32 maxEntries ; 00625 Uint32 ipsId ; 00626 Uint32 ipsEventNo ; 00627 } LINKCFG_Mpcs ; 00628 00629 00630 /** ============================================================================ 00631 * @name LINKCFG_Log 00632 * 00633 * @brief This structure defines the configuration structure for the LOG 00634 * component. 00635 * 00636 * @param gdMsgqPut 00637 * GPP->DSP MSG Transfer - MSGQ_put call. 00638 * @param gdMsgqSendInt 00639 * GPP->DSP MSG Transfer - GPP sends interrupt. 00640 * @param gdMsgqIsr 00641 * GPP->DSP MSG Transfer - DSP receives interrupt. 00642 * @param gdMsgqQue 00643 * GPP->DSP MSG Transfer - Message queued at DSP. 00644 * @param dgMsgqPut 00645 * DSP->GPP MSG Transfer - MSGQ_put call. 00646 * @param dgMsgqSendInt 00647 * DSP->GPP MSG Transfer - DSP sends interrupt. 00648 * @param dgMsgqIsr 00649 * DSP->GPP MSG Transfer - GPP receives interrupt. 00650 * @param dgMsgqQue 00651 * DSP->GPP MSG Transfer - Message queued at GPP. 00652 * @param gdChnlIssueStart 00653 * GPP->DSP CHNL Transfer - Entering inside ISSUE call. 00654 * @param gdChnlIssueQue 00655 * GPP->DSP CHNL Transfer - ISSUE: Buffer is queued in internal 00656 * structure on GPP. 00657 * @param gdChnlIssueCompl 00658 * GPP->DSP CHNL Transfer - ISSUE call completed. 00659 * @param gdChnlXferStart 00660 * GPP->DSP CHNL Transfer - Initiating a buffer transfer by GPP. 00661 * @param gdChnlXferProcess 00662 * GPP->DSP CHNL Transfer - Actual transfer of buffer is going to 00663 * take place. 00664 * @param gdChnlXferCompl 00665 * GPP->DSP CHNL Transfer - Buffer transfer is complete. 00666 * @param gdChnlReclStart 00667 * GPP->DSP CHNL Transfer - Entering RECLAIM call. 00668 * @param gdChnlReclPend 00669 * GPP->DSP CHNL Transfer - RECLAIM: Wait on a semaphore. 00670 * @param gdChnlReclPost 00671 * GPP->DSP CHNL Transfer - RECLAIM: Posting the Semaphore. 00672 * @param gdChnlReclCompl 00673 * GPP->DSP CHNL Transfer - RECLAIM call completed. 00674 * @param dgChnlIssueQue 00675 * DSP->GPP CHNL Transfer - ISSUE: Buffer is queued in internal 00676 * structure on DSP. 00677 * @param dgChnlXferStart 00678 * DSP->GPP CHNL Transfer - Initiating a buffer transfer by DSP. 00679 * @param dgChnlXferProcess 00680 * DSP->GPP CHNL Transfer - Actual transfer of buffer is going to 00681 * take place. 00682 * @param dgChnlXferCompl 00683 * DSP->GPP CHNL Transfer - Buffer transfer is complete. 00684 * @param dgChnlReclPend 00685 * DSP->GPP CHNL Transfer - RECLAIM: Wait on a semaphore. 00686 * @param dgChnlReclPost 00687 * DSP->GPP CHNL Transfer - RECLAIM: Posting the Semaphore. 00688 * @param msgIdRangeStart 00689 * MSG ID range: lower limit. 00690 * @param msgIdRangeEnd 00691 * MSG ID range: upper limit. 00692 * ============================================================================ 00693 */ 00694 typedef struct LINKCFG_Log_tag { 00695 Bool gdMsgqPut ; 00696 Bool gdMsgqSendInt ; 00697 Bool gdMsgqIsr ; 00698 Bool gdMsgqQue ; 00699 00700 Bool dgMsgqPut ; 00701 Bool dgMsgqSendInt ; 00702 Bool dgMsgqIsr ; 00703 Bool dgMsgqQue ; 00704 00705 Bool gdChnlIssueStart ; 00706 Bool gdChnlIssueQue ; 00707 Bool gdChnlIssueCompl ; 00708 00709 Bool gdChnlXferStart ; 00710 Bool gdChnlXferProcess ; 00711 Bool gdChnlXferCompl ; 00712 00713 Bool gdChnlReclStart ; 00714 Bool gdChnlReclPend ; 00715 Bool gdChnlReclPost ; 00716 Bool gdChnlReclCompl ; 00717 00718 Bool dgChnlIssueQue ; 00719 00720 Bool dgChnlXferStart ; 00721 Bool dgChnlXferProcess ; 00722 Bool dgChnlXferCompl ; 00723 00724 Bool dgChnlReclPend ; 00725 Bool dgChnlReclPost ; 00726 00727 Uint32 msgIdRangeStart ; 00728 Uint32 msgIdRangeEnd ; 00729 } LINKCFG_Log ; 00730 00731 00732 /** ============================================================================ 00733 * @name LINKCFG_DspConfig 00734 * 00735 * @brief Defines the object containing all configuration items for DSPs. 00736 * 00737 * @param dspObject 00738 * DSP object. 00739 * @param numDrvs 00740 * Number of link Drv specified in configuration database. 00741 * @param linkDrvObjects 00742 * Pointer to the array of link Drv objects. 00743 * @param numMemTables 00744 * Number of MEM tables specified in configuration database. 00745 * @param memTables 00746 * Pointer to the array of memory information table arrays. 00747 * @param numIpsTables 00748 * Number of IPS tables. 00749 * @param ipsTables 00750 * Pointer to the array of IPS table arrays. 00751 * @param numPoolTables 00752 * Number of POOL tables. 00753 * @param poolTables 00754 * Pointer to the array of POOL table arrays. 00755 * @param numDataTables 00756 * Number of data tables. 00757 * @param dataTables 00758 * Pointer to the array data table arrays. 00759 * @param numMqts 00760 * Number of Message Queue Transports. 00761 * @param mqtObjects 00762 * Pointer to the array of MQT objects. 00763 * @param numRingIo 00764 * Number of RingIO tables. 00765 * @param ringIoObjects 00766 * Pointer to the array of RingIO tables. 00767 * @param numMpList 00768 * Number of MPLIST tables. 00769 * @param mplistObjects 00770 * Pointer to the array of MPLIST tables. 00771 * @param numMpcs 00772 * Number of MPCS tables. 00773 * @param mpcsObjects 00774 * Pointer to the array of MPCS tables. 00775 * @param logObject 00776 * Pointer to the LOG object. 00777 * ============================================================================ 00778 */ 00779 typedef struct LINKCFG_DspConfig_tag { 00780 LINKCFG_Dsp * dspObject ; 00781 Uint32 numDrvs ; 00782 LINKCFG_LinkDrv * linkDrvObjects ; 00783 Uint32 numMemTables ; 00784 LINKCFG_MemEntry ** memTables ; 00785 00786 Uint32 numIpsTables ; 00787 LINKCFG_Ips ** ipsTables ; 00788 00789 Uint32 numPoolTables ; 00790 LINKCFG_Pool ** poolTables ; 00791 00792 Uint32 numDataTables ; 00793 LINKCFG_DataDrv ** dataTables ; 00794 00795 Uint32 numMqts ; 00796 LINKCFG_Mqt * mqtObjects ; 00797 00798 Uint32 numRingIo ; 00799 LINKCFG_RingIo * ringIoObjects ; 00800 00801 Uint32 numMpList ; 00802 LINKCFG_MpList * mplistObjects ; 00803 00804 Uint32 numMpcs ; 00805 LINKCFG_Mpcs * mpcsObjects ; 00806 00807 LINKCFG_Log * logObject ; 00808 } LINKCFG_DspConfig ; 00809 00810 00811 /** ============================================================================ 00812 * @name LINKCFG_Object 00813 * 00814 * @brief This structure defines the configuration structure for the system. 00815 * 00816 * @param gppObject 00817 * Pointer to the GPP specific configuration object. 00818 * @param linkObjects 00819 * DSP/BIOS LINK configuration structures. 00820 * ============================================================================ 00821 */ 00822 typedef struct LINKCFG_Object_tag { 00823 LINKCFG_Gpp * gppObject ; 00824 LINKCFG_DspConfig * dspConfigs [MAX_DSPS] ; 00825 } LINKCFG_Object ; 00826 00827 00828 #if defined (__cplusplus) 00829 } 00830 #endif /* defined (__cplusplus) */ 00831 00832 00833 #endif /* !defined (LINKCFGDEFS_H) */