00001 /** ============================================================================ 00002 * @file c64xxdefs.h 00003 * 00004 * @path $(DSPLINK)/dsp/inc/C674X/ 00005 * 00006 * @brief Defines which are common to C64XX device type. 00007 * 00008 * @ver 1.65.00.03 00009 * ============================================================================ 00010 * @copyright Copyright (C) 2002-2009, Texas Instruments Incorporated - 00011 * http://www.ti.com/ 00012 * 00013 * Redistribution and use in source and binary forms, with or without 00014 * modification, are permitted provided that the following conditions 00015 * are met: 00016 * 00017 * * Redistributions of source code must retain the above copyright 00018 * notice, this list of conditions and the following disclaimer. 00019 * 00020 * * Redistributions in binary form must reproduce the above copyright 00021 * notice, this list of conditions and the following disclaimer in the 00022 * documentation and/or other materials provided with the distribution. 00023 * 00024 * * Neither the name of Texas Instruments Incorporated nor the names of 00025 * its contributors may be used to endorse or promote products derived 00026 * from this software without specific prior written permission. 00027 * 00028 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00029 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 00030 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 00031 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 00032 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 00033 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 00034 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 00035 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 00036 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 00037 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 00038 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00039 * ============================================================================ 00040 */ 00041 00042 00043 #if !defined (C64XXDEFS_H) 00044 #define C64XXDEFS_H 00045 00046 00047 #if defined (__cplusplus) 00048 extern "C" { 00049 #endif /* defined (__cplusplus) */ 00050 00051 00052 /** ============================================================================ 00053 * @const SHMEM_INTERFACE 00054 * 00055 * @brief Interface number for shared memory interface. 00056 * ============================================================================ 00057 */ 00058 #define SHMEM_INTERFACE 0 00059 00060 /** ============================================================================ 00061 * @const PCI_INTERFACE 00062 * 00063 * @brief Interface number for PCI interface. 00064 * ============================================================================ 00065 */ 00066 #define PCI_INTERFACE 1 00067 00068 /** ============================================================================ 00069 * @const VLYNQ_INTERFACE 00070 * 00071 * @brief Interface number for VLYNQ interface. 00072 * ============================================================================ 00073 */ 00074 #define VLYNQ_INTERFACE 2 00075 00076 /** ============================================================================ 00077 * @const DSPLINK_BUF_ALIGN 00078 * 00079 * @brief Value of Align parameter to alloc/create calls. 00080 * ============================================================================ 00081 */ 00082 #define DSPLINK_BUF_ALIGN 128 00083 00084 /** ============================================================================ 00085 * @const DSP_MAUSIZE 00086 * 00087 * @brief Size of the DSP MAU (in bytes). 00088 * ============================================================================ 00089 */ 00090 #define DSP_MAUSIZE 1 00091 00092 /** ============================================================================ 00093 * @const CACHE_L2_LINESIZE 00094 * 00095 * @brief Line size of DSP L2 cache (in bytes). 00096 * ============================================================================ 00097 */ 00098 #define CACHE_L2_LINESIZE 128 00099 00100 /** ============================================================================ 00101 * @const ADD_PADDING 00102 * 00103 * @brief Macro to add padding to a structure. 00104 * ============================================================================ 00105 */ 00106 #define ADD_PADDING(padVar, count) Uint16 padVar [count] ; 00107 00108 #if defined (MSGQ_COMPONENT) 00109 /** ============================================================================ 00110 * @const PCPYMQT_CTRLMSG_SIZE 00111 * 00112 * @brief Size (in MADUs) of the control messages used by the PCPY MQT. 00113 * ============================================================================ 00114 */ 00115 #define PCPYMQT_CTRLMSG_SIZE 128 00116 00117 /** ============================================================================ 00118 * @const ZCPYMQT_CTRLMSG_SIZE 00119 * 00120 * @brief Size (in MADUs) of the control messages used by the ZCPY MQT. 00121 * ============================================================================ 00122 */ 00123 #define ZCPYMQT_CTRLMSG_SIZE 128 00124 #endif /* defined (MSGQ_COMPONENT) */ 00125 00126 /* ============================================================================ 00127 * @const DSPLINK_ALIGN 00128 * 00129 * @brief Macro to align a number to a specified value. 00130 * x: The number to be aligned 00131 * y: The value that the number should be aligned to. 00132 * ============================================================================ 00133 */ 00134 #define DSPLINK_ALIGN(x, y) (Uint32)((Uint32)((x + y - 1) / y) * y) 00135 00136 /** ============================================================================ 00137 * @const DSPLINK_16BIT_PADDING 00138 * 00139 * @brief Padding required for alignment of a 16-bit value (for L2 cache) 00140 * in 16-bit words. 00141 * ============================================================================ 00142 */ 00143 #define DSPLINK_16BIT_PADDING ((CACHE_L2_LINESIZE - sizeof (Uint16)) / 2) 00144 00145 /** ============================================================================ 00146 * @const DSPLINK_32BIT_PADDING 00147 * 00148 * @brief Padding required for alignment of a 32-bit value (for L2 cache) 00149 * in 16-bit words. 00150 * ============================================================================ 00151 */ 00152 #define DSPLINK_32BIT_PADDING ((CACHE_L2_LINESIZE - sizeof (Uint32)) / 2) 00153 00154 /** ============================================================================ 00155 * @const DSPLINK_BOOL_PADDING 00156 * 00157 * @brief Padding required for alignment of a Boolean value (for L2 cache) 00158 * in 16-bit words. 00159 * ============================================================================ 00160 */ 00161 #define DSPLINK_BOOL_PADDING ((CACHE_L2_LINESIZE - sizeof (Bool)) / 2) 00162 00163 /** ============================================================================ 00164 * @const DSPLINK_PTR_PADDING 00165 * 00166 * @brief Padding required for alignment of a pointer value (for L2 cache) 00167 * in 16-bit words. 00168 * ============================================================================ 00169 */ 00170 #define DSPLINK_PTR_PADDING ((CACHE_L2_LINESIZE - sizeof (Void *)) / 2) 00171 00172 /** ============================================================================ 00173 * @const DRV_PADDING 00174 * 00175 * @brief Padding required for DSP L2 cache line alignment within DRV 00176 * control structure. 00177 * ============================================================================ 00178 */ 00179 #define DRV_CTRL_SIZE ( (sizeof (Uint32) * 23) \ 00180 + (sizeof (Char) * DSP_MAX_STRLEN) \ 00181 + (sizeof (Uint32) * 4)) 00182 00183 #define DRV_PADDING (( DSPLINK_ALIGN (DRV_CTRL_SIZE, \ 00184 DSPLINK_BUF_ALIGN) \ 00185 - DRV_CTRL_SIZE) / 2) 00186 00187 /** ============================================================================ 00188 * @const IPS_EVENT_ENTRY_PADDING 00189 * 00190 * @brief Padding length for IPS event entry. 00191 * ============================================================================ 00192 */ 00193 #define IPS_EVENT_ENTRY_PADDING ( (CACHE_L2_LINESIZE \ 00194 - ((sizeof (Uint32)) * 3)) / 2) 00195 00196 /** ============================================================================ 00197 * @const IPS_CTRL_PADDING 00198 * 00199 * @brief Padding length for IPS control structure. 00200 * ============================================================================ 00201 */ 00202 #define IPS_CTRL_PADDING ( (CACHE_L2_LINESIZE \ 00203 - (sizeof (Void *) * 6)) / 2) 00204 00205 /** ============================================================================ 00206 * @const DSPLINKIPS_CTRL_PADDING 00207 * 00208 * @brief Padding length for the DSPLINKIPS shared configuration structure. 00209 * ============================================================================ 00210 */ 00211 #define DSPLINKIPS_CTRL_PADDING ( (CACHE_L2_LINESIZE \ 00212 - ( sizeof (Uint32) \ 00213 + (sizeof (Uint32) * 6))) / 2) 00214 00215 #if defined (POOL_COMPONENT) 00216 /** ============================================================================ 00217 * @const DSPLINKPOOL_CTRL_PADDING 00218 * 00219 * @brief Padding length for the DSPLINKPOOL shared configuration structure. 00220 * ============================================================================ 00221 */ 00222 #define DSPLINKPOOL_CTRL_PADDING ( (CACHE_L2_LINESIZE \ 00223 - ( sizeof (Uint32) \ 00224 + (sizeof (Uint32) * 5))) / 2) 00225 #endif /* if defined (POOL_COMPONENT) */ 00226 00227 #if defined (MSGQ_COMPONENT) 00228 /** ============================================================================ 00229 * @const DSPLINKMQT_CTRL_PADDING 00230 * 00231 * @brief Padding length for the MQT shared configuration structure. 00232 * ============================================================================ 00233 */ 00234 #define DSPLINKMQT_CTRL_PADDING ( (CACHE_L2_LINESIZE \ 00235 - ( sizeof (Uint32) \ 00236 + (sizeof (Uint32) * 5))) / 2) 00237 #endif /* if defined (MSGQ_COMPONENT) */ 00238 00239 #if defined (CHNL_COMPONENT) 00240 /** ============================================================================ 00241 * @const DSPLINKDATA_CTRL_PADDING 00242 * 00243 * @brief Padding length for the Data driver shared configuration structure. 00244 * ============================================================================ 00245 */ 00246 #define DSPLINKDATA_CTRL_PADDING ( (CACHE_L2_LINESIZE \ 00247 - ( sizeof (Uint32) \ 00248 + (sizeof (Uint32) * 9))) / 2) 00249 #endif /* if defined (CHNL_COMPONENT) */ 00250 00251 #if defined (MPCS_COMPONENT) 00252 /** ============================================================================ 00253 * @const MPCSOBJ_PROC_PADDING 00254 * 00255 * @brief Padding required for alignment of MPCS object for a processor (for 00256 * L2 cache) in 16-bit words. 00257 * ============================================================================ 00258 */ 00259 #define MPCSOBJ_PROC_PADDING ((CACHE_L2_LINESIZE - sizeof (MPCS_ProcObj)) / 2) 00260 00261 /** ============================================================================ 00262 * @const MPCS_CTRL_PADDING 00263 * 00264 * @brief Padding length for MPCS control region. 00265 * ============================================================================ 00266 */ 00267 #define MPCS_CTRL_PADDING (( CACHE_L2_LINESIZE \ 00268 - ( (sizeof (Uint32) * 5) \ 00269 + (sizeof (Void *)))) / 2) 00270 00271 /** ============================================================================ 00272 * @const MPCS_ENTRY_PADDING 00273 * 00274 * @brief Padding length for MPCS_Entry. 00275 * ============================================================================ 00276 */ 00277 #define MPCS_ENTRY_PADDING (( CACHE_L2_LINESIZE \ 00278 - ( (sizeof (Ptr)) \ 00279 + (DSP_MAX_STRLEN * sizeof (Char)) \ 00280 + (sizeof (Uint16) * 2))) / 2) 00281 00282 /** ============================================================================ 00283 * @const MPCS_TURN_PADDING 00284 * 00285 * @brief Pad length for MPCS turn member. 00286 * ============================================================================ 00287 */ 00288 #define MPCS_TURN_PADDING (( CACHE_L2_LINESIZE \ 00289 - (sizeof (Uint16))) /2) 00290 #endif /* if defined (MPCS_COMPONENT) */ 00291 00292 #if defined (RINGIO_COMPONENT) 00293 /** ============================================================================ 00294 * @const RINGIO_ENTRY_PADDING 00295 * 00296 * @brief Padding length for RingIO_Entry. 00297 * ============================================================================ 00298 */ 00299 #define RINGIO_ENTRY_PADDING (( CACHE_L2_LINESIZE \ 00300 - ( (RINGIO_NAME_MAX_LEN * sizeof (Char)) \ 00301 + (sizeof (Void *) * 2) \ 00302 + (sizeof (Uint16) * 5))) / 2) 00303 00304 /** ============================================================================ 00305 * @const RINGIO_CTRL_PADDING 00306 * 00307 * @brief Padding length for RINGIO control region. 00308 * ============================================================================ 00309 */ 00310 #define RINGIO_CTRL_PADDING (( CACHE_L2_LINESIZE \ 00311 - ( (sizeof (Uint32) * 5) \ 00312 + (sizeof (Void *)))) / 2) 00313 00314 /* ============================================================================ 00315 * @const RINGIO_CLIENT_PADDING 00316 * 00317 * @brief Padding length for Client structure. 00318 * ============================================================================ 00319 */ 00320 #define RINGIO_CLIENT_PADDING (( CACHE_L2_LINESIZE \ 00321 - ( sizeof (RingIO_BufPtr)* 2 \ 00322 + sizeof (Uint32) * 11 \ 00323 + sizeof (RingIO_NotifyFunc) \ 00324 + sizeof (RingIO_NotifyParam) \ 00325 + sizeof (RingIO_ControlStruct *) \ 00326 + sizeof (Void *) \ 00327 + sizeof (Uint16))) / 2) 00328 00329 /** ============================================================================ 00330 * @const RINGIO_CONTROLSTRUCT_PADDING 00331 * 00332 * @brief Padding length for control structure. 00333 * ============================================================================ 00334 */ 00335 #define RINGIO_CONTROLSTRUCT_PADDING (( CACHE_L2_LINESIZE \ 00336 - ( (sizeof (Uint32) * 14) \ 00337 + sizeof (Int32) \ 00338 + (sizeof (RingIO_BufPtr)* 2) \ 00339 + sizeof (Void *))) /2) 00340 #endif /* if defined (RINGIO_COMPONENT) */ 00341 00342 #if defined (MPLIST_COMPONENT) 00343 /** ============================================================================ 00344 * @const MPLIST_ENTRY_PADDING 00345 * 00346 * @brief Padding length for MPLIST_Entry. 00347 * ============================================================================ 00348 */ 00349 #define MPLIST_ENTRY_PADDING (( CACHE_L2_LINESIZE \ 00350 - ( (DSP_MAX_STRLEN * sizeof (Char)) \ 00351 + (sizeof (Void *)) \ 00352 + (sizeof (Uint16) * 2))) / 2) \ 00353 00354 /** ============================================================================ 00355 * @const MPLIST_CTRL_PADDING 00356 * 00357 * @brief Padding length for MPLIST control region. 00358 * ============================================================================ 00359 */ 00360 #define MPLIST_CTRL_PADDING (( CACHE_L2_LINESIZE \ 00361 - ( (sizeof (Uint32) * 5) \ 00362 + (sizeof (Void *)))) / 2) 00363 00364 /** ============================================================================ 00365 * @const MPLIST_LIST_PADDING 00366 * 00367 * @brief Padding length for MPLIST_List. 00368 * ============================================================================ 00369 */ 00370 #define MPLIST_LIST_PADDING (( CACHE_L2_LINESIZE \ 00371 - (sizeof (Void *) * 2)) / 2) 00372 #endif /* if defined (MPLIST_COMPONENT) */ 00373 00374 00375 #if defined (__cplusplus) 00376 } 00377 #endif /* defined (__cplusplus) */ 00378 00379 00380 #endif /* !defined (C64XXDEFS_H) */