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Defines | |
#define | C64XXDEFS_H |
#define | SHMEM_INTERFACE 0 |
Interface number for shared memory interface. ============================================================================. | |
#define | PCI_INTERFACE 1 |
Interface number for PCI interface. ============================================================================. | |
#define | VLYNQ_INTERFACE 2 |
Interface number for VLYNQ interface. ============================================================================. | |
#define | DSPLINK_BUF_ALIGN 128 |
Value of Align parameter to alloc/create calls. ============================================================================. | |
#define | DSP_MAUSIZE 1 |
Size of the DSP MAU (in bytes). ============================================================================. | |
#define | CACHE_L2_LINESIZE 128 |
Line size of DSP L2 cache (in bytes). ============================================================================. | |
#define | ADD_PADDING(padVar, count) Uint16 padVar [count] ; |
Macro to add padding to a structure. ============================================================================. | |
#define | DSPLINK_ALIGN(x, y) (Uint32)((Uint32)((x + y - 1) / y) * y) |
#define | DSPLINK_16BIT_PADDING ((CACHE_L2_LINESIZE - sizeof (Uint16)) / 2) |
Padding required for alignment of a 16-bit value (for L2 cache) in 16-bit words. ============================================================================. | |
#define | DSPLINK_32BIT_PADDING ((CACHE_L2_LINESIZE - sizeof (Uint32)) / 2) |
Padding required for alignment of a 32-bit value (for L2 cache) in 16-bit words. ============================================================================. | |
#define | DSPLINK_BOOL_PADDING ((CACHE_L2_LINESIZE - sizeof (Bool)) / 2) |
Padding required for alignment of a Boolean value (for L2 cache) in 16-bit words. ============================================================================. | |
#define | DSPLINK_PTR_PADDING ((CACHE_L2_LINESIZE - sizeof (Void *)) / 2) |
Padding required for alignment of a pointer value (for L2 cache) in 16-bit words. ============================================================================. | |
#define | DRV_CTRL_SIZE |
Padding required for DSP L2 cache line alignment within DRV control structure. ============================================================================. | |
#define | DRV_PADDING |
#define | IPS_EVENT_ENTRY_PADDING |
Padding length for IPS event entry. ============================================================================. | |
#define | IPS_CTRL_PADDING |
Padding length for IPS control structure. ============================================================================. | |
#define | DSPLINKIPS_CTRL_PADDING |
Padding length for the DSPLINKIPS shared configuration structure. ============================================================================. |
============================================================================
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
* Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ============================================================================
Definition in file c64xxdefs.h.
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Macro to add padding to a structure. ============================================================================. ============================================================================
Definition at line 106 of file c64xxdefs.h. |
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Definition at line 44 of file c64xxdefs.h. |
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Line size of DSP L2 cache (in bytes). ============================================================================. ============================================================================
Definition at line 98 of file c64xxdefs.h. |
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Value: ( (sizeof (Uint32) * 23) \ + (sizeof (Char) * DSP_MAX_STRLEN) \ + (sizeof (Uint32) * 4)) ============================================================================
Definition at line 179 of file c64xxdefs.h. |
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Value: (( DSPLINK_ALIGN (DRV_CTRL_SIZE, \ DSPLINK_BUF_ALIGN) \ - DRV_CTRL_SIZE) / 2) Definition at line 183 of file c64xxdefs.h. |
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Size of the DSP MAU (in bytes). ============================================================================. ============================================================================
Definition at line 90 of file c64xxdefs.h. |
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Padding required for alignment of a 16-bit value (for L2 cache) in 16-bit words. ============================================================================. ============================================================================
Definition at line 143 of file c64xxdefs.h. |
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Padding required for alignment of a 32-bit value (for L2 cache) in 16-bit words. ============================================================================. ============================================================================
Definition at line 152 of file c64xxdefs.h. |
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Definition at line 134 of file c64xxdefs.h. |
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Padding required for alignment of a Boolean value (for L2 cache) in 16-bit words. ============================================================================. ============================================================================
Definition at line 161 of file c64xxdefs.h. |
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Value of Align parameter to alloc/create calls. ============================================================================. ============================================================================
Definition at line 82 of file c64xxdefs.h. |
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Padding required for alignment of a pointer value (for L2 cache) in 16-bit words. ============================================================================. ============================================================================
Definition at line 170 of file c64xxdefs.h. |
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Value: ( (CACHE_L2_LINESIZE \ - ( sizeof (Uint32) \ + (sizeof (Uint32) * 6))) / 2) ============================================================================
Definition at line 211 of file c64xxdefs.h. |
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Value: ( (CACHE_L2_LINESIZE \ - (sizeof (Void *) * 6)) / 2) ============================================================================
Definition at line 202 of file c64xxdefs.h. |
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Value: ( (CACHE_L2_LINESIZE \ - ((sizeof (Uint32)) * 3)) / 2) ============================================================================
Definition at line 193 of file c64xxdefs.h. |
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Interface number for PCI interface. ============================================================================. ============================================================================
Definition at line 66 of file c64xxdefs.h. |
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Interface number for shared memory interface. ============================================================================. ============================================================================
Definition at line 58 of file c64xxdefs.h. |
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Interface number for VLYNQ interface. ============================================================================. ============================================================================
Definition at line 74 of file c64xxdefs.h. |