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dm6437_hal_vlynq.h File Reference

Hardware Abstraction Layer for PC-DM64LC VLYNQ interface. Defines interfaces to initialize the VLYNQ interface. More...

#include <dsplink.h>
#include <dm6437_hal.h>

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Data Structures

struct  DM6437_devRegs_tag
struct  DM6437_pllRegs_tag
struct  DM6437_ddrRegs
struct  DM6437_pscRegs_tag
struct  DM6437_pciRegs
struct  DM6437_vlynqRegs
struct  DM6437_paramEntry_tags
struct  DRA44XGEM_EDMA3_CCRL_DraRegs
struct  DRA44XGEM_EDMA3_CCRL_QueevtentryRegs
struct  DRA44XGEM_EDMA3_CCRL_ShadowRegs
struct  DRA44XGEM_edmaRegs
struct  DM6437_HalVlynqPhyObj_tag

DM6437_devRegs

Register Overlay Structure for Device config registers. ============================================================================

============================================================================

typedef DM6437_devRegs_tag DM6437_devRegs

DM6437_pllRegs

Register Overlay Structure for PLL. ============================================================================

============================================================================

typedef DM6437_pllRegs_tag DM6437_pllRegs

DM6437_pscRegs

Register Overlay Structure for PSC. ============================================================================

============================================================================

typedef DM6437_pscRegs_tag DM6437_pscRegs

DM6437_pciRegs

PCI Back end register overlay structure. ============================================================================

============================================================================

typedef DM6437_pciRegs DM6437_pciRegs

DM6437_vlynqRegs

VLYNQ register structure. ============================================================================

============================================================================

typedef DM6437_vlynqRegs DM6437_vlynqRegs

DRA44XGEM_paramEntry

Register Overlay Structure for PARAMENTRY. ============================================================================

============================================================================

typedef DM6437_paramEntry_tags DRA44XGEM_paramEntry

Defines

#define DM6437_HAL_VLYNQ_H
#define VLYNQ_DMA_MAXTHROUGHPUT   10u
 Approx. Maximum through put of VLYNQ interface (100Mhz * 4 /32) words (32bit)/Sec. ============================================================================.
#define LPSC_GEM   39u
 Module number for GEM. ============================================================================.
#define LPSC_EDMA_TPCC   2u
 Module number for EDMA TPCC. ============================================================================.
#define LPSC_EDMA_TPTC0   3u
 Module number for EDMA TPTC0. ============================================================================.
#define LPSC_EDMA_TPTC1   4u
 Module number for EDMA TPTC1. ============================================================================.
#define LPSC_DDR   13u
 Module number for DDR. ============================================================================.
#define DM6437_DEVREG_BASE   0x00440000u
 Base address of Device config registers. ============================================================================.
#define DM6437_PLL0REG_BASE   0x00440800u
 Base address of PLL0 registers. ============================================================================.
#define DM6437_PLL1REG_BASE   0x00440C00u
 Base address of PLL1 registers. ============================================================================.
#define DM6437_EDMAREG_BASE   0x400000u
 Base address of EDMA registers. ============================================================================.
#define DM6437_DDRREG_BASE   0x20000000u
 Base address of DDR PHY registers. ============================================================================.
#define DM6437_PSCREG_BASE   0x00441000u
 Base address of PSC registers. ============================================================================.
#define DM6437_PCIREG_BASE   0x0041A000u
 Base address of PCI backend registers. ============================================================================.
#define DM6437_PEERVLYNQREG_BASE   0x00601000u
 Base address of VLYNQ registers. ============================================================================.
#define DM6437_SOFTINT1_MASK   0x02000000u
 Mask for generating soft int1 (DSP->GPP) ============================================================================.
#define DM6437_LRESET_MASK   0x00000100u
 Mask for reseting/releasing GEM. ============================================================================.
#define DM6437_INTSTATUS_MASK   0x00080000u
 Bitmask for Interrupt status (DSP->GPP) ============================================================================.
#define DM6437_BOOTCMPLTBC_MASK   0x00000001u
 Bitmask for Setting BC bit in BOOTCOMPLT register. ============================================================================.
#define DM6437_VLYNQ_WINDOWSIZE   0x04000000u
 Total size exposed by VLYNQ 64MB. ============================================================================.
#define DRA44XGEM_EDMA_REGBASE   0x01C00000u
 Base Address of DRA44xGEM EDMA controller registers. ============================================================================.


Detailed Description

Hardware Abstraction Layer for PC-DM64LC VLYNQ interface. Defines interfaces to initialize the VLYNQ interface.

============================================================================

Path:
/db/swcoe_asp/DSPLINK_Build/dsplink_linux_1_65_00_03/dsplink/gpp/inc/sys/arch/DM6437/
Version:
1.65.00.03 ============================================================================
Copyright:
Copyright (C) 2002-2009, Texas Instruments Incorporated - http://www.ti.com/
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.

* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

* Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ============================================================================

Definition in file dm6437_hal_vlynq.h.


Define Documentation

#define DM6437_BOOTCMPLTBC_MASK   0x00000001u
 

Bitmask for Setting BC bit in BOOTCOMPLT register. ============================================================================.

============================================================================

Constant:
DM6437_BOOTCMPLTBC_MASK

Definition at line 203 of file dm6437_hal_vlynq.h.

#define DM6437_DDRREG_BASE   0x20000000u
 

Base address of DDR PHY registers. ============================================================================.

============================================================================

Constant:
DM6437_DDRREG_BASE

Definition at line 147 of file dm6437_hal_vlynq.h.

#define DM6437_DEVREG_BASE   0x00440000u
 

Base address of Device config registers. ============================================================================.

============================================================================

Constant:
DM6437_DEVREG_BASE

Definition at line 115 of file dm6437_hal_vlynq.h.

#define DM6437_EDMAREG_BASE   0x400000u
 

Base address of EDMA registers. ============================================================================.

============================================================================

Constant:
DM6437_EDMAREG_BASE

Definition at line 139 of file dm6437_hal_vlynq.h.

#define DM6437_HAL_VLYNQ_H
 

Definition at line 45 of file dm6437_hal_vlynq.h.

#define DM6437_INTSTATUS_MASK   0x00080000u
 

Bitmask for Interrupt status (DSP->GPP) ============================================================================.

============================================================================

Constant:
DM6437_INTSTATUS_MASK

Definition at line 195 of file dm6437_hal_vlynq.h.

#define DM6437_LRESET_MASK   0x00000100u
 

Mask for reseting/releasing GEM. ============================================================================.

============================================================================

Constant:
DM6437_LRESET_MASK

Definition at line 187 of file dm6437_hal_vlynq.h.

#define DM6437_PCIREG_BASE   0x0041A000u
 

Base address of PCI backend registers. ============================================================================.

============================================================================

Constant:
DM6437_PCIREG_BASE

Definition at line 163 of file dm6437_hal_vlynq.h.

#define DM6437_PEERVLYNQREG_BASE   0x00601000u
 

Base address of VLYNQ registers. ============================================================================.

============================================================================

Constant:
DM6437_PEERVLYNQREG_BASE

Definition at line 171 of file dm6437_hal_vlynq.h.

#define DM6437_PLL0REG_BASE   0x00440800u
 

Base address of PLL0 registers. ============================================================================.

============================================================================

Constant:
DM6437_PLLREG_BASE

Definition at line 123 of file dm6437_hal_vlynq.h.

#define DM6437_PLL1REG_BASE   0x00440C00u
 

Base address of PLL1 registers. ============================================================================.

============================================================================

Constant:
DM6437_PLLREG_BASE

Definition at line 131 of file dm6437_hal_vlynq.h.

#define DM6437_PSCREG_BASE   0x00441000u
 

Base address of PSC registers. ============================================================================.

============================================================================

Constant:
DM6437_PSCREG_BASE

Definition at line 155 of file dm6437_hal_vlynq.h.

#define DM6437_SOFTINT1_MASK   0x02000000u
 

Mask for generating soft int1 (DSP->GPP) ============================================================================.

============================================================================

Constant:
DM6437_SOFTINT1_MASK

Definition at line 179 of file dm6437_hal_vlynq.h.

#define DM6437_VLYNQ_WINDOWSIZE   0x04000000u
 

Total size exposed by VLYNQ 64MB. ============================================================================.

============================================================================

Constant:
DM6437_VLYNQ_WINDOWSIZE

Definition at line 211 of file dm6437_hal_vlynq.h.

#define DRA44XGEM_EDMA_REGBASE   0x01C00000u
 

Base Address of DRA44xGEM EDMA controller registers. ============================================================================.

============================================================================

Constant:
DRA44XGEM_EDMA_REGBASE

Definition at line 219 of file dm6437_hal_vlynq.h.

#define LPSC_DDR   13u
 

Module number for DDR. ============================================================================.

============================================================================

Constant:
LPSC_DDR

Definition at line 107 of file dm6437_hal_vlynq.h.

#define LPSC_EDMA_TPCC   2u
 

Module number for EDMA TPCC. ============================================================================.

============================================================================

Constant:
LPSC_EDMA_TPCC

Definition at line 83 of file dm6437_hal_vlynq.h.

#define LPSC_EDMA_TPTC0   3u
 

Module number for EDMA TPTC0. ============================================================================.

============================================================================

Constant:
LPSC_EDMA_TPTC0

Definition at line 91 of file dm6437_hal_vlynq.h.

#define LPSC_EDMA_TPTC1   4u
 

Module number for EDMA TPTC1. ============================================================================.

============================================================================

Constant:
LPSC_EDMA_TPTC1

Definition at line 99 of file dm6437_hal_vlynq.h.

#define LPSC_GEM   39u
 

Module number for GEM. ============================================================================.

============================================================================

Constant:
LPSC_GEM

Definition at line 75 of file dm6437_hal_vlynq.h.

#define VLYNQ_DMA_MAXTHROUGHPUT   10u
 

Approx. Maximum through put of VLYNQ interface (100Mhz * 4 /32) words (32bit)/Sec. ============================================================================.

============================================================================

Constant:
VLYNQ_DMA_MAXTHROUGHPUT

Definition at line 67 of file dm6437_hal_vlynq.h.


Typedef Documentation

typedef struct DM6437_devRegs_tag DM6437_devRegs
 

typedef struct DM6437_pciRegs DM6437_pciRegs
 

typedef struct DM6437_pllRegs_tag DM6437_pllRegs
 

typedef struct DM6437_pscRegs_tag DM6437_pscRegs
 

typedef struct DM6437_vlynqRegs DM6437_vlynqRegs
 

typedef struct DM6437_paramEntry_tags DRA44XGEM_paramEntry
 


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