#include <dsplink.h>
#include <dm6437_hal.h>
Include dependency graph for dm6437_hal_pci.h:
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Go to the source code of this file.
Data Structures | |
struct | DM6437_devRegs_tag |
struct | DM6437_pllRegs_tag |
struct | DM6437_ddrRegs |
struct | DM6437_pscRegs_tag |
struct | DM6437_paramEntry_tags |
struct | DM6437_edmaRegs_tag |
struct | DM6437_pciRegs_tag |
struct | DM6437_HalPciPhyObj_tag |
DM6437_devRegs | |
Register Overlay Structure for Device config registers. ============================================================================
============================================================================ | |
typedef DM6437_devRegs_tag | DM6437_devRegs |
DM6437_pllRegs | |
Register Overlay Structure for PLL. ============================================================================
============================================================================ | |
typedef DM6437_pllRegs_tag | DM6437_pllRegs |
DM6437_pscRegs | |
Register Overlay Structure for PSC. ============================================================================
============================================================================ | |
typedef DM6437_pscRegs_tag | DM6437_pscRegs |
DM6437_paramEntry | |
Register Overlay Structure for PARAMENTRY. ============================================================================
============================================================================ | |
typedef DM6437_paramEntry_tags | DM6437_paramEntry |
DM6437_edmaRegs | |
Register Overlay Structure for EDMA. ============================================================================
============================================================================ | |
typedef DM6437_edmaRegs_tag | DM6437_edmaRegs |
DM6437_pciRegs | |
PCI Back end register overlay structure. ============================================================================
============================================================================ | |
typedef DM6437_pciRegs_tag | DM6437_pciRegs |
Defines | |
#define | DM6437_HAL_PCI_H |
#define | NUM_BARS 6 |
Number of BAR registers. ============================================================================. | |
#define | PCI33_DMA_MAXTHROUGHPUT 132u |
Maximum through put of PCI interface. ============================================================================. | |
#define | DDR_REGS_BAR_NO 1u |
Number for the BAR register used for DDR EMIF register access. ============================================================================. | |
#define | CFG_REGS_BAR_NO 2u |
Number for the BAR register used for register access. ============================================================================. | |
#define | RWMEM_BAR_NO 4u |
Number for the BAR register used for L1DRAM access. ============================================================================. | |
#define | SHMEM_BAR_NO 5u |
Number for the BAR register used for shared memory access. ============================================================================. | |
#define | LPSC_GEM 39u |
Module number for GEM. ============================================================================. | |
#define | LPSC_EDMA_TPCC 2u |
Module number for EDMA TPCC. ============================================================================. | |
#define | LPSC_EDMA_TPTC0 3u |
Module number for EDMA TPTC0. ============================================================================. | |
#define | LPSC_EDMA_TPTC1 4u |
Module number for EDMA TPTC1. ============================================================================. | |
#define | LPSC_EDMA_TPTC2 5u |
Module number for EDMA TPTC2. ============================================================================. | |
#define | LPSC_DDR 13u |
Module number for DDR. ============================================================================. | |
#define | DM6437_PCIMEM_BASE 0x30000000u |
PCI memory base in GEM memory space. ============================================================================. | |
#define | DM6437_DEVREG_BASE 0x40000u |
Base address of Device config registers. ============================================================================. | |
#define | DM6437_PLL0REG_BASE 0x40800u |
Base address of PLL0 registers. ============================================================================. | |
#define | DM6437_PLL1REG_BASE 0x40C00u |
Base address of PLL1 registers. ============================================================================. | |
#define | DM6437_EDMAREG_BASE 0x0u |
Base address of EDMA registers. ============================================================================. | |
#define | DM6437_DDRREG_BASE 0x0u |
Base address of DDR PHY registers. ============================================================================. | |
#define | DM6437_PSCREG_BASE 0x41000u |
Base address of PSC registers. ============================================================================. | |
#define | DM6437_PCIREG_BASE 0x1A000u |
Base address of PCI backend registers. ============================================================================. | |
#define | DM6437_SOFTINT0_MASK 0x01000000u |
Mask for generating soft int0 (DSP->GPP) ============================================================================. | |
#define | DM6437_SOFTINT1_MASK 0x02000000u |
Mask for generating soft int1 (GPP->DSP) ============================================================================. | |
#define | DM6437_LRESET_MASK 0x00000100u |
Mask for reseting/releasing GEM. ============================================================================. | |
#define | DM6437_INTSTATUS_MASK 0x00080000u |
Bitmask for Interrupt status (DSP->GPP) ============================================================================. | |
#define | DM6437_BOOTCMPLTBC_MASK 0x00000001u |
Bitmask for Setting BC bit in BOOTCOMPLT register. ============================================================================. | |
#define | DM6437_PCIADLEN 0x00800000u |
Length each segment of addressable PCI Space.. ============================================================================. | |
#define | DM6437_PCIADWRBITMASK 0xFF800000u |
Mask indicating writeable bits in PCI Address Window registers. ============================================================================. | |
#define | DM6437_PAGEWRBITMASK 0xFF800000u |
Mask indicating writeable bits in PCI Base Address Mask Register5. ============================================================================. |
============================================================================
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
* Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ============================================================================
Definition in file dm6437_hal_pci.h.
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Number for the BAR register used for register access. ============================================================================. ============================================================================
Definition at line 90 of file dm6437_hal_pci.h. |
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Number for the BAR register used for DDR EMIF register access. ============================================================================. ============================================================================
Definition at line 82 of file dm6437_hal_pci.h. |
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Bitmask for Setting BC bit in BOOTCOMPLT register. ============================================================================. ============================================================================
Definition at line 258 of file dm6437_hal_pci.h. |
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Base address of DDR PHY registers. ============================================================================. ============================================================================
Definition at line 202 of file dm6437_hal_pci.h. |
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Base address of Device config registers. ============================================================================. ============================================================================
Definition at line 170 of file dm6437_hal_pci.h. |
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Base address of EDMA registers. ============================================================================. ============================================================================
Definition at line 194 of file dm6437_hal_pci.h. |
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Definition at line 45 of file dm6437_hal_pci.h. |
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Bitmask for Interrupt status (DSP->GPP) ============================================================================. ============================================================================
Definition at line 250 of file dm6437_hal_pci.h. |
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Mask for reseting/releasing GEM. ============================================================================. ============================================================================
Definition at line 242 of file dm6437_hal_pci.h. |
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Mask indicating writeable bits in PCI Base Address Mask Register5. ============================================================================. ============================================================================
Definition at line 282 of file dm6437_hal_pci.h. |
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Length each segment of addressable PCI Space.. ============================================================================. ============================================================================
Definition at line 266 of file dm6437_hal_pci.h. |
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Mask indicating writeable bits in PCI Address Window registers. ============================================================================. ============================================================================
Definition at line 274 of file dm6437_hal_pci.h. |
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PCI memory base in GEM memory space. ============================================================================. ============================================================================
Definition at line 162 of file dm6437_hal_pci.h. |
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Base address of PCI backend registers. ============================================================================. ============================================================================
Definition at line 218 of file dm6437_hal_pci.h. |
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Base address of PLL0 registers. ============================================================================. ============================================================================
Definition at line 178 of file dm6437_hal_pci.h. |
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Base address of PLL1 registers. ============================================================================. ============================================================================
Definition at line 186 of file dm6437_hal_pci.h. |
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Base address of PSC registers. ============================================================================. ============================================================================
Definition at line 210 of file dm6437_hal_pci.h. |
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Mask for generating soft int0 (DSP->GPP) ============================================================================. ============================================================================
Definition at line 226 of file dm6437_hal_pci.h. |
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Mask for generating soft int1 (GPP->DSP) ============================================================================. ============================================================================
Definition at line 234 of file dm6437_hal_pci.h. |
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Module number for DDR. ============================================================================. ============================================================================
Definition at line 154 of file dm6437_hal_pci.h. |
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Module number for EDMA TPCC. ============================================================================. ============================================================================
Definition at line 122 of file dm6437_hal_pci.h. |
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Module number for EDMA TPTC0. ============================================================================. ============================================================================
Definition at line 130 of file dm6437_hal_pci.h. |
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Module number for EDMA TPTC1. ============================================================================. ============================================================================
Definition at line 138 of file dm6437_hal_pci.h. |
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Module number for EDMA TPTC2. ============================================================================. ============================================================================
Definition at line 146 of file dm6437_hal_pci.h. |
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Module number for GEM. ============================================================================. ============================================================================
Definition at line 114 of file dm6437_hal_pci.h. |
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Number of BAR registers. ============================================================================. ============================================================================
Definition at line 66 of file dm6437_hal_pci.h. |
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Maximum through put of PCI interface. ============================================================================. ============================================================================
Definition at line 74 of file dm6437_hal_pci.h. |
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Number for the BAR register used for L1DRAM access. ============================================================================. ============================================================================
Definition at line 98 of file dm6437_hal_pci.h. |
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Number for the BAR register used for shared memory access. ============================================================================. ============================================================================
Definition at line 106 of file dm6437_hal_pci.h. |
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