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dm6437_hal_vlynq.h

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00001 /** ============================================================================
00002  *  @file   dm6437_hal_vlynq.h
00003  *
00004  *  @path   $(DSPLINK)/gpp/inc/sys/arch/DM6437/
00005  *
00006  *  @brief  Hardware Abstraction Layer for PC-DM64LC VLYNQ interface.
00007  *          Defines interfaces to initialize the VLYNQ interface.
00008  *
00009  *  @ver    1.65.00.03
00010  *  ============================================================================
00011  *  @copyright Copyright (C) 2002-2009, Texas Instruments Incorporated -
00012  *  http://www.ti.com/
00013  *
00014  *  Redistribution and use in source and binary forms, with or without
00015  *  modification, are permitted provided that the following conditions
00016  *  are met:
00017  *  
00018  *  *  Redistributions of source code must retain the above copyright
00019  *     notice, this list of conditions and the following disclaimer.
00020  *  
00021  *  *  Redistributions in binary form must reproduce the above copyright
00022  *     notice, this list of conditions and the following disclaimer in the
00023  *     documentation and/or other materials provided with the distribution.
00024  *  
00025  *  *  Neither the name of Texas Instruments Incorporated nor the names of
00026  *     its contributors may be used to endorse or promote products derived
00027  *     from this software without specific prior written permission.
00028  *  
00029  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00030  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
00031  *  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
00032  *  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
00033  *  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
00034  *  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
00035  *  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
00036  *  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
00037  *  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
00038  *  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
00039  *  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00040  *  ============================================================================
00041  */
00042 
00043 
00044 #if !defined (DM6437_HAL_VLYNQ_H)
00045 #define DM6437_HAL_VLYNQ_H
00046 
00047 
00048 /*  ----------------------------------- DSP/BIOS Link               */
00049 #include <dsplink.h>
00050 
00051 /*  ----------------------------------- Hardware Abstraction Layer  */
00052 #include <dm6437_hal.h>
00053 
00054 
00055 #if defined (__cplusplus)
00056 extern "C" {
00057 #endif /* if defined (__cplusplus) */
00058 
00059 
00060 /** ============================================================================
00061  *  @const  VLYNQ_DMA_MAXTHROUGHPUT
00062  *
00063  *  @brief  Approx. Maximum through put of VLYNQ interface
00064  *          (100Mhz * 4 /32) words (32bit)/Sec.
00065  *  ============================================================================
00066  */
00067 #define VLYNQ_DMA_MAXTHROUGHPUT     10u
00068 
00069 /** ============================================================================
00070  *  @const   LPSC_GEM
00071  *
00072  *  @brief   Module number for GEM.
00073  *  ============================================================================
00074  */
00075 #define LPSC_GEM                    39u
00076 
00077 /** ============================================================================
00078  *  @const   LPSC_EDMA_TPCC
00079  *
00080  *  @brief   Module number for EDMA TPCC.
00081  *  ============================================================================
00082  */
00083 #define LPSC_EDMA_TPCC              2u
00084 
00085 /** ============================================================================
00086  *  @const   LPSC_EDMA_TPTC0
00087  *
00088  *  @brief   Module number for EDMA TPTC0.
00089  *  ============================================================================
00090  */
00091 #define LPSC_EDMA_TPTC0             3u
00092 
00093 /** ============================================================================
00094  *  @const   LPSC_EDMA_TPTC1
00095  *
00096  *  @brief   Module number for EDMA TPTC1.
00097  *  ============================================================================
00098  */
00099 #define LPSC_EDMA_TPTC1             4u
00100 
00101 /** ============================================================================
00102  *  @const   LPSC_DDR
00103  *
00104  *  @brief   Module number for DDR.
00105  *  ============================================================================
00106  */
00107 #define LPSC_DDR                    13u
00108 
00109 /** ============================================================================
00110  *  @const   DM6437_DEVREG_BASE
00111  *
00112  *  @brief   Base address of Device config registers.
00113  *  ============================================================================
00114  */
00115 #define DM6437_DEVREG_BASE          0x00440000u
00116 
00117 /** ============================================================================
00118  *  @const   DM6437_PLLREG_BASE
00119  *
00120  *  @brief   Base address of PLL0 registers.
00121  *  ============================================================================
00122  */
00123 #define DM6437_PLL0REG_BASE         0x00440800u
00124 
00125 /** ============================================================================
00126  *  @const   DM6437_PLLREG_BASE
00127  *
00128  *  @brief   Base address of PLL1 registers.
00129  *  ============================================================================
00130  */
00131 #define DM6437_PLL1REG_BASE         0x00440C00u
00132 
00133 /** ============================================================================
00134  *  @const   DM6437_EDMAREG_BASE
00135  *
00136  *  @brief   Base address of EDMA registers.
00137  *  ============================================================================
00138  */
00139 #define DM6437_EDMAREG_BASE         0x400000u
00140 
00141 /** ============================================================================
00142  *  @const   DM6437_DDRREG_BASE
00143  *
00144  *  @brief   Base address of DDR PHY registers.
00145  *  ============================================================================
00146  */
00147 #define DM6437_DDRREG_BASE          0x20000000u
00148 
00149 /** ============================================================================
00150  *  @const   DM6437_PSCREG_BASE
00151  *
00152  *  @brief   Base address of PSC registers.
00153  *  ============================================================================
00154  */
00155 #define DM6437_PSCREG_BASE          0x00441000u
00156 
00157 /** ============================================================================
00158  *  @const   DM6437_PCIREG_BASE
00159  *
00160  *  @brief   Base address of PCI backend registers.
00161  *  ============================================================================
00162  */
00163 #define DM6437_PCIREG_BASE          0x0041A000u
00164 
00165 /** ============================================================================
00166  *  @const   DM6437_PEERVLYNQREG_BASE
00167  *
00168  *  @brief   Base address of VLYNQ registers.
00169  *  ============================================================================
00170  */
00171 #define DM6437_PEERVLYNQREG_BASE    0x00601000u
00172 
00173 /** ============================================================================
00174  *  @const   DM6437_SOFTINT1_MASK
00175  *
00176  *  @brief   Mask for generating soft int1 (DSP->GPP)
00177  *  ============================================================================
00178  */
00179 #define DM6437_SOFTINT1_MASK        0x02000000u
00180 
00181 /** ============================================================================
00182  *  @const   DM6437_LRESET_MASK
00183  *
00184  *  @brief   Mask for reseting/releasing GEM.
00185  *  ============================================================================
00186  */
00187 #define DM6437_LRESET_MASK          0x00000100u
00188 
00189 /** ============================================================================
00190  *  @const   DM6437_INTSTATUS_MASK
00191  *
00192  *  @brief   Bitmask for Interrupt status (DSP->GPP)
00193  *  ============================================================================
00194  */
00195 #define DM6437_INTSTATUS_MASK       0x00080000u
00196 
00197 /** ============================================================================
00198  *  @const   DM6437_BOOTCMPLTBC_MASK
00199  *
00200  *  @brief   Bitmask for Setting BC bit in BOOTCOMPLT register.
00201  *  ============================================================================
00202  */
00203 #define DM6437_BOOTCMPLTBC_MASK     0x00000001u
00204 
00205 /** ============================================================================
00206  *  @const   DM6437_VLYNQ_WINDOWSIZE
00207  *
00208  *  @brief   Total size exposed by VLYNQ 64MB.
00209  *  ============================================================================
00210  */
00211 #define DM6437_VLYNQ_WINDOWSIZE     0x04000000u
00212 
00213 /** ============================================================================
00214  *  @const   DRA44XGEM_EDMA_REGBASE
00215  *
00216  *  @brief   Base Address of DRA44xGEM EDMA controller registers.
00217  *  ============================================================================
00218  */
00219 #define DRA44XGEM_EDMA_REGBASE      0x01C00000u
00220 
00221 
00222 /** ============================================================================
00223  *  @name   DM6437_devRegs
00224  *
00225  *  @brief  Register Overlay Structure for Device config registers.
00226  *  ============================================================================
00227  */
00228 typedef struct DM6437_devRegs_tag {
00229     volatile Uint32 PINMUX0       ;
00230     volatile Uint32 PINMUX1       ;
00231     volatile Uint32 DSPBOOTADDR   ;
00232     volatile Uint32 BOOTCMPLT     ;
00233     volatile Uint32 RSVD0         ;
00234     volatile Uint32 BOOTCFG       ;
00235     volatile Uint32 VDD1P0V_ADJ   ;
00236     volatile Uint32 VDD1P2V_ADJ   ;
00237     volatile Uint32 DDR_SLEW      ;
00238     volatile Uint32 PERIPHEN      ;
00239     volatile Uint32 DEVICE_ID     ;
00240     volatile Uint32 DAC_DEMEN     ;
00241     volatile Uint32 UHPICTL       ;
00242     volatile Uint32 RSVD1 [2]     ;
00243     volatile Uint32 MSTPRI0       ;
00244     volatile Uint32 MSTPRI1       ;
00245     volatile Uint32 VPSS_CLK_CTRL ;
00246     volatile Uint32 VDD3P3V_PWRDN ;
00247     volatile Uint32 DFT_ENABLE    ;
00248     volatile Uint32 SEC_SCAN_REG  ;
00249     volatile Uint32 SEC_TEST_REG  ;
00250     volatile Uint32 SEC_TAP_CTL   ;
00251     volatile Uint32 PUBLIC_KEY0   ;
00252     volatile Uint32 PUBLIC_KEY1   ;
00253     volatile Uint32 PUBLIC_KEY2   ;
00254     volatile Uint32 PUBLIC_KEY3   ;
00255     volatile Uint32 VLYNQ_DELAY   ;
00256     volatile Uint32 SEC_PSEUDO0   ;
00257     volatile Uint32 SEC_PSEUDO1   ;
00258     volatile Uint32 RSVD2 [3]     ;
00259     volatile Uint32 TIMERCTL      ;
00260     volatile Uint32 TPTCCCFG      ;
00261     volatile Uint32 RSVD3         ;
00262 } DM6437_devRegs ;
00263 
00264 /** ============================================================================
00265  *  @name   DM6437_pllRegs
00266  *
00267  *  @brief  Register Overlay Structure for PLL.
00268  *  ============================================================================
00269  */
00270 typedef struct DM6437_pllRegs_tag {
00271     volatile Uint32 PID         ;
00272     volatile Uint8  RSVD0 [220] ;
00273     volatile Uint32 FUSERR      ;
00274     volatile Uint32 RSTYPE      ;
00275     volatile Uint32 RSTDEF      ;
00276     volatile Uint8  RSVD1 [20]  ;
00277     volatile Uint32 PLLCTL      ;
00278     volatile Uint32 OCSEL       ;
00279     volatile Uint32 SECCTL      ;
00280     volatile Uint8  RSVD2 [4]   ;
00281     volatile Uint32 PLLM        ;
00282     volatile Uint32 PREDIV      ;
00283     volatile Uint32 PLLDIV1     ;
00284     volatile Uint32 PLLDIV2     ;
00285     volatile Uint32 PLLDIV3     ;
00286     volatile Uint32 OSCDIV1     ;
00287     volatile Uint32 POSTDIV     ;
00288     volatile Uint32 BPDIV       ;
00289     volatile Uint32 WAKEUP      ;
00290     volatile Uint8  RSVD3 [4]   ;
00291     volatile Uint32 PLLCMD      ;
00292     volatile Uint32 PLLSTAT     ;
00293     volatile Uint32 ALNCTL      ;
00294     volatile Uint32 DCHANGE     ;
00295     volatile Uint32 CKEN        ;
00296     volatile Uint32 CKSTAT      ;
00297     volatile Uint32 SYSTAT      ;
00298     volatile Uint8  RSVD4 [12]  ;
00299     volatile Uint32 PLLDIV4     ;
00300     volatile Uint32 PLLDIV5     ;
00301     volatile Uint32 PLLDIV6     ;
00302     volatile Uint32 PLLDIV7     ;
00303     volatile Uint32 PLLDIV8     ;
00304 } DM6437_pllRegs ;
00305 
00306 /** ============================================================================
00307  *  @name   DM6437_ddrRegs
00308  *
00309  *  @brief  Register Overlay Structure for DDR.
00310  *  ============================================================================
00311  */
00312 typedef struct  {
00313     volatile Uint32 ERCSR       ;
00314     volatile Uint32 SDRSTAT     ;
00315     volatile Uint32 SDBCR       ;
00316     volatile Uint32 SDRCR       ;
00317     volatile Uint32 SDTIMR      ;
00318     volatile Uint32 SDTIMR2     ;
00319     volatile Uint8  RSVD0 [8]   ;
00320     volatile Uint32 VBPR        ;
00321     volatile Uint8  RSVD1 [4]   ;
00322     volatile Uint32 VBCFG1      ;
00323     volatile Uint32 VBCFG2      ;
00324     volatile Uint8  RSVD2 [16]  ;
00325     volatile Uint32 PERFC1R     ;
00326     volatile Uint32 PERFC2R     ;
00327     volatile Uint32 PCCR        ;
00328     volatile Uint32 PCMRSR      ;
00329     volatile Uint8  RSVD3 [48]  ;
00330     volatile Uint32 ASYNCCS2CR  ;
00331     volatile Uint32 ASYNCCS3CR  ;
00332     volatile Uint32 ASYNCCS4CR  ;
00333     volatile Uint32 ASYNCCS5CR  ;
00334     volatile Uint8  RSVD4 [16]  ;
00335     volatile Uint32 AWCCR       ;
00336     volatile Uint8  RSVD5 [28]  ;
00337     volatile Uint32 IRR         ;
00338     volatile Uint32 IMR         ;
00339     volatile Uint32 IMSR        ;
00340     volatile Uint32 IMCR        ;
00341     volatile Uint8  RSVD6 [16]  ;
00342     volatile Uint32 DDRPHYREV   ;
00343     volatile Uint32 DDRPHYCR    ;
00344     volatile Uint32 DDRPHYSR    ;
00345     volatile Uint8  RSVD7 [4]   ;
00346     volatile Uint32 VTPCTRL     ;
00347     volatile Uint32 VTPSTAT     ;
00348 } DM6437_ddrRegs ;
00349 
00350 /** ============================================================================
00351  *  @name   DM6437_pscRegs
00352  *
00353  *  @brief  Register Overlay Structure for PSC.
00354  *  ============================================================================
00355  */
00356 typedef struct DM6437_pscRegs_tag {
00357     volatile Uint32 PID          ;
00358     volatile Uint8  RSVD0 [12]   ;
00359     volatile Uint32 GBLCTL       ;
00360     volatile Uint8  RSVD1 [4]    ;
00361     volatile Uint32 INTEVAL      ;
00362     volatile Uint8  RSVD2 [36]   ;
00363     volatile Uint32 ERRPR0       ;
00364     volatile Uint32 ERRPR1       ;
00365     volatile Uint8  RSVD3 [8]    ;
00366     volatile Uint32 ERRCR0       ;
00367     volatile Uint32 ERRCR1       ;
00368     volatile Uint8  RSVD4 [8]    ;
00369     volatile Uint32 PERRPR       ;
00370     volatile Uint8  RSVD5 [4]    ;
00371     volatile Uint32 PERRCR       ;
00372     volatile Uint8  RSVD6 [4]    ;
00373     volatile Uint32 EPCPR        ;
00374     volatile Uint8  RSVD7 [4]    ;
00375     volatile Uint32 EPCR         ;
00376     volatile Uint8  RSVD8 [132]  ;
00377     volatile Uint32 RAILSTAT     ;
00378     volatile Uint32 RAILCTL      ;
00379     volatile Uint32 RAILSEL      ;
00380     volatile Uint8  RSVD9 [20]   ;
00381     volatile Uint32 PTCMD        ;
00382     volatile Uint8  RSVD10 [4]   ;
00383     volatile Uint32 PTSTAT       ;
00384     volatile Uint8  RSVD11 [212] ;
00385     volatile Uint32 PDSTAT [41]  ;
00386     volatile Uint8  RSVD12 [92]  ;
00387     volatile Uint32 PDCTL [41]   ;
00388     volatile Uint8  RSVD13 [348] ;
00389     volatile Uint32 MRSTOUT [2]  ;
00390     volatile Uint8  RSVD14 [8]   ;
00391     volatile Uint32 MCKOUT [2]   ;
00392     volatile Uint8  RSVD15 [232] ;
00393     volatile Uint32 MDCFG [41]   ;
00394     volatile Uint8  RSVD16 [348] ;
00395     volatile Uint32 MDSTAT [41]  ;
00396     volatile Uint8  RSVD17 [348] ;
00397     volatile Uint32 MDCTL [41]   ;
00398 } DM6437_pscRegs ;
00399 
00400 /** ============================================================================
00401  *  @name   DM6437_pciRegs
00402  *
00403  *  @brief  PCI Back end register overlay structure.
00404  *  ============================================================================
00405  */
00406 typedef struct DM6437_pciRegs {
00407     volatile Uint32 PCIREVID       ;
00408     volatile Uint8  RSVD0 [12]     ;
00409     volatile Uint32 PCISTATSET     ;
00410     volatile Uint32 PCISTATCLR     ;
00411     volatile Uint8  RSVD1 [8]      ;
00412     volatile Uint32 PCIHINTSET     ;
00413     volatile Uint32 PCIHINTCLR     ;
00414     volatile Uint8  RSVD2 [8]      ;
00415     volatile Uint32 PCIBINTSET     ;
00416     volatile Uint32 PCIBINTCLR     ;
00417     volatile Uint32 PCIBCLKMGT     ;
00418     volatile Uint8  RSVD3 [196]    ;
00419     volatile Uint32 PCIVENDEVMIR   ;
00420     volatile Uint32 PCICSRMIR      ;
00421     volatile Uint32 PCICLREVMIR    ;
00422     volatile Uint32 PCICLINEMIR    ;
00423     volatile Uint32 PCIBAR0MSK     ;
00424     volatile Uint32 PCIBAR1MSK     ;
00425     volatile Uint32 PCIBAR2MSK     ;
00426     volatile Uint32 PCIBAR3MSK     ;
00427     volatile Uint32 PCIBAR4MSK     ;
00428     volatile Uint32 PCIBAR5MSK     ;
00429     volatile Uint8  RSVD4[4]       ;
00430     volatile Uint32 PCISUBIDMIR    ;
00431     volatile Uint8  RSVD5 [4]      ;
00432     volatile Uint32 PCICPBPTRMIR   ;
00433     volatile Uint8  RSVD6 [4]      ;
00434     volatile Uint32 PCILGINTMIR    ;
00435     volatile Uint8  RSVD7 [64]     ;
00436     volatile Uint32 PCISLVCNTL     ;
00437     volatile Uint8  RSVD8 [60]     ;
00438     volatile Uint32 PCIBAR0TRL     ;
00439     volatile Uint32 PCIBAR1TRL     ;
00440     volatile Uint32 PCIBAR2TRL     ;
00441     volatile Uint32 PCIBAR3TRL     ;
00442     volatile Uint32 PCIBAR4TRL     ;
00443     volatile Uint32 PCIBAR5TRL     ;
00444     volatile Uint8  RSVD9 [8]      ;
00445     volatile Uint32 PCIBARMIR [6]  ;
00446     volatile Uint8  RSVD10 [264]   ;
00447     volatile Uint32 PCIMCFGDAT     ;
00448     volatile Uint32 PCIMCFGADR     ;
00449     volatile Uint32 PCIMCFGCMD     ;
00450     volatile Uint8  RSVD11 [4]     ;
00451     volatile Uint32 PCIMSTCFG      ;
00452     volatile Uint32 PCIADDSUB [32] ;
00453     volatile Uint32 PCIVENDEVPRG   ;
00454     volatile Uint32 PCICMDSTATPRG  ;
00455     volatile Uint32 PCICLREVPRG    ;
00456     volatile Uint32 PCISUBIDPRG    ;
00457     volatile Uint32 PCIMAXLGPRG    ;
00458     volatile Uint32 PCILRSTREG     ;
00459     volatile Uint32 PCICFGDONE     ;
00460     volatile Uint32 PCIBAR0MPRG    ;
00461     volatile Uint32 PCIBAR1MPRG    ;
00462     volatile Uint32 PCIBAR2MPRG    ;
00463     volatile Uint32 PCIBAR3MPRG    ;
00464     volatile Uint32 PCIBAR4MPRG    ;
00465     volatile Uint32 PCIBAR5MPRG    ;
00466     volatile Uint32 PCIBAR0PRG     ;
00467     volatile Uint32 PCIBAR1PRG     ;
00468     volatile Uint32 PCIBAR2PRG     ;
00469     volatile Uint32 PCIBAR3PRG     ;
00470     volatile Uint32 PCIBAR4PRG     ;
00471     volatile Uint32 PCIBAR5PRG     ;
00472     volatile Uint32 PCIBAR0TRLPRG  ;
00473     volatile Uint32 PCIBAR1TRLPRG  ;
00474     volatile Uint32 PCIBAR2TRLPRG  ;
00475     volatile Uint32 PCIBAR3TRLPRG  ;
00476     volatile Uint32 PCIBAR4TRLPRG  ;
00477     volatile Uint32 PCIBAR5TRLPRG  ;
00478     volatile Uint32 PCIBASENPRG    ;
00479 } DM6437_pciRegs ;
00480 
00481 
00482 /** ============================================================================
00483  *  @name   DM6437_vlynqRegs
00484  *
00485  *  @brief  VLYNQ register structure.
00486  *  ============================================================================
00487  */
00488 typedef struct DM6437_vlynqRegs {
00489     volatile Uint32 LOCAL_REVID       ;
00490     volatile Uint32 LOCAL_CTRL        ;
00491     volatile Uint32 LOCAL_STAT        ;
00492     volatile Uint32 LOCAL_INTPRI      ;
00493     volatile Uint32 LOCAL_INTSTATCLR  ;
00494     volatile Uint32 LOCAL_INTPENDSET  ;
00495     volatile Uint32 LOCAL_INTPTR      ;
00496     volatile Uint32 LOCAL_XAM         ;
00497     volatile Uint32 LOCAL_RAMS1       ;
00498     volatile Uint32 LOCAL_RAMO1       ;
00499     volatile Uint32 LOCAL_RAMS2       ;
00500     volatile Uint32 LOCAL_RAMO2       ;
00501     volatile Uint32 LOCAL_RAMS3       ;
00502     volatile Uint32 LOCAL_RAMO3       ;
00503     volatile Uint32 LOCAL_RAMS4       ;
00504     volatile Uint32 LOCAL_RAMO4       ;
00505     volatile Uint32 LOCAL_CHIPVER     ;
00506     volatile Uint32 LOCAL_AUTNGO      ;
00507     volatile Uint32 reserved [14]     ;
00508     volatile Uint32 PEER_REVID        ;
00509     volatile Uint32 PEER_CTRL         ;
00510     volatile Uint32 PEER_STAT         ;
00511     volatile Uint32 PEER_INTPRI       ;
00512     volatile Uint32 PEER_INTSTATCLR   ;
00513     volatile Uint32 PEER_INTPENDSET   ;
00514     volatile Uint32 PEER_INTPTR       ;
00515     volatile Uint32 PEER_XAM          ;
00516     volatile Uint32 PEER_RAMS1        ;
00517     volatile Uint32 PEER_RAMO1        ;
00518     volatile Uint32 PEER_RAMS2        ;
00519     volatile Uint32 PEER_RAMO2        ;
00520     volatile Uint32 PEER_RAMS3        ;
00521     volatile Uint32 PEER_RAMO3        ;
00522     volatile Uint32 PEER_RAMS4        ;
00523     volatile Uint32 PEER_RAMO4        ;
00524     volatile Uint32 PEER_CHIPVER      ;
00525     volatile Uint32 PEER_AUTNGO       ;
00526     volatile Uint32 PEER_MANNGO       ;
00527     volatile Uint32 PEER_NGOSTAT      ;
00528     volatile Uint32 PEER_INTVEC0      ;
00529     volatile Uint32 PEER_INTVEC1      ;
00530 } DM6437_vlynqRegs ;
00531 
00532 /** ============================================================================
00533  *  @name   DRA44XGEM_paramEntry
00534  *
00535  *  @brief  Register Overlay Structure for PARAMENTRY.
00536  *  ============================================================================
00537  */
00538 typedef struct DM6437_paramEntry_tags {
00539     volatile Uint32 OPTION        ;
00540     volatile Uint32 SRC           ;
00541     volatile Uint32 A_B_CNT       ;
00542     volatile Uint32 DST           ;
00543     volatile Uint32 SRC_DST_BIDX  ;
00544     volatile Uint32 LINK_BCNTRLD  ;
00545     volatile Uint32 SRC_DST_CIDX  ;
00546     volatile Uint32 CCNT          ;
00547 } DRA44XGEM_paramEntry ;
00548 
00549 /** ============================================================================
00550  *  @name   DRA44XGEM_EDMA3_CCRL_DraRegs
00551  *
00552  *  @brief  Register Overlay Structure for DRA.
00553  *  ============================================================================
00554  */
00555 typedef struct  {
00556     volatile Uint32 DRAE;
00557     volatile Uint32 DRAEH;
00558 } DRA44XGEM_EDMA3_CCRL_DraRegs;
00559 
00560 /** ============================================================================
00561  *  @name   DRA44XGEM_EDMA3_CCRL_QueevtentryRegs
00562  *
00563  *  @brief  Register Overlay Structure for QUEEVTENTRY.
00564  *  ============================================================================
00565  */
00566 typedef struct  {
00567     volatile Uint32 QUEEVT_ENTRY;
00568 } DRA44XGEM_EDMA3_CCRL_QueevtentryRegs;
00569 
00570 /** ============================================================================
00571  *  @name   DRA44XGEM_EDMA3_CCRL_ShadowRegs
00572  *
00573  *  @brief  Register Overlay Structure for SHADOW.
00574  *  ============================================================================
00575  */
00576 typedef struct  {
00577     volatile Uint32 ER;
00578     volatile Uint32 ERH;
00579     volatile Uint32 ECR;
00580     volatile Uint32 ECRH;
00581     volatile Uint32 ESR;
00582     volatile Uint32 ESRH;
00583     volatile Uint32 CER;
00584     volatile Uint32 CERH;
00585     volatile Uint32 EER;
00586     volatile Uint32 EERH;
00587     volatile Uint32 EECR;
00588     volatile Uint32 EECRH;
00589     volatile Uint32 EESR;
00590     volatile Uint32 EESRH;
00591     volatile Uint32 SER;
00592     volatile Uint32 SERH;
00593     volatile Uint32 SECR;
00594     volatile Uint32 SECRH;
00595     volatile Uint8  RSVD0[8];
00596     volatile Uint32 IER;
00597     volatile Uint32 IERH;
00598     volatile Uint32 IECR;
00599     volatile Uint32 IECRH;
00600     volatile Uint32 IESR;
00601     volatile Uint32 IESRH;
00602     volatile Uint32 IPR;
00603     volatile Uint32 IPRH;
00604     volatile Uint32 ICR;
00605     volatile Uint32 ICRH;
00606     volatile Uint32 IEVAL;
00607     volatile Uint8  RSVD1[4];
00608     volatile Uint32 QER;
00609     volatile Uint32 QEER;
00610     volatile Uint32 QEECR;
00611     volatile Uint32 QEESR;
00612     volatile Uint32 QSER;
00613     volatile Uint32 QSECR;
00614     volatile Uint8  RSVD2[360];
00615 } DRA44XGEM_EDMA3_CCRL_ShadowRegs;
00616 
00617 /** ============================================================================
00618  *  @name   DRA44XGEM_edmaRegs
00619  *
00620  *  @brief  Register Overlay Structure for EDMA.
00621  *  ============================================================================
00622  */
00623 typedef struct  {
00624     volatile Uint32 REV;
00625     volatile Uint32 CCCFG;
00626     volatile Uint8  RSVD0[248];
00627     volatile Uint32 DCHMAP[64];
00628     volatile Uint32 QCHMAP[8];
00629     volatile Uint8  RSVD1[32];
00630     volatile Uint32 DMAQNUM[8];
00631     volatile Uint32 QDMAQNUM;
00632     volatile Uint8  RSVD2[28];
00633     volatile Uint32 QUETCMAP;
00634     volatile Uint32 QUEPRI;
00635     volatile Uint8  RSVD3[120];
00636     volatile Uint32 EMR;
00637     volatile Uint32 EMRH;
00638     volatile Uint32 EMCR;
00639     volatile Uint32 EMCRH;
00640     volatile Uint32 QEMR;
00641     volatile Uint32 QEMCR;
00642     volatile Uint32 CCERR;
00643     volatile Uint32 CCERRCLR;
00644     volatile Uint32 EEVAL;
00645     volatile Uint8  RSVD4[28];
00646     DRA44XGEM_EDMA3_CCRL_DraRegs DRA[8];
00647     volatile Uint32 QRAE[8];
00648     volatile Uint8  RSVD5[96];
00649     DRA44XGEM_EDMA3_CCRL_QueevtentryRegs QUEEVTENTRY[8][16];
00650     volatile Uint32 QSTAT[8];
00651     volatile Uint32 QWMTHRA;
00652     volatile Uint32 QWMTHRB;
00653     volatile Uint8  RSVD6[24];
00654     volatile Uint32 CCSTAT;
00655     volatile Uint8  RSVD7[188];
00656     volatile Uint32 AETCTL;
00657     volatile Uint32 AETSTAT;
00658     volatile Uint32 AETCMD;
00659     volatile Uint8  RSVD8[244];
00660     volatile Uint32 MPFAR;
00661     volatile Uint32 MPFSR;
00662     volatile Uint32 MPFCR;
00663     volatile Uint32 MPPAG;
00664     volatile Uint32 MPPA[8];
00665     volatile Uint8  RSVD9[2000];
00666     volatile Uint32 ER;
00667     volatile Uint32 ERH;
00668     volatile Uint32 ECR;
00669     volatile Uint32 ECRH;
00670     volatile Uint32 ESR;
00671     volatile Uint32 ESRH;
00672     volatile Uint32 CER;
00673     volatile Uint32 CERH;
00674     volatile Uint32 EER;
00675     volatile Uint32 EERH;
00676     volatile Uint32 EECR;
00677     volatile Uint32 EECRH;
00678     volatile Uint32 EESR;
00679     volatile Uint32 EESRH;
00680     volatile Uint32 SER;
00681     volatile Uint32 SERH;
00682     volatile Uint32 SECR;
00683     volatile Uint32 SECRH;
00684     volatile Uint8  RSVD10[8];
00685     volatile Uint32 IER;
00686     volatile Uint32 IERH;
00687     volatile Uint32 IECR;
00688     volatile Uint32 IECRH;
00689     volatile Uint32 IESR;
00690     volatile Uint32 IESRH;
00691     volatile Uint32 IPR;
00692     volatile Uint32 IPRH;
00693     volatile Uint32 ICR;
00694     volatile Uint32 ICRH;
00695     volatile Uint32 IEVAL;
00696     volatile Uint8  RSVD11[4];
00697     volatile Uint32 QER;
00698     volatile Uint32 QEER;
00699     volatile Uint32 QEECR;
00700     volatile Uint32 QEESR;
00701     volatile Uint32 QSER;
00702     volatile Uint32 QSECR;
00703     volatile Uint8  RSVD12[3944];
00704     DRA44XGEM_EDMA3_CCRL_ShadowRegs SHADOW[8];
00705     volatile Uint8 RSVD13[4096];
00706     DRA44XGEM_paramEntry PARAMENTRY[512];
00707 } DRA44XGEM_edmaRegs;
00708 
00709 /** ============================================================================
00710  *  @name   DM6437_HalVlynqPhyObj_tag
00711  *
00712  *  @brief  Physical Interface object.
00713  *
00714  *  @param  region1Addr
00715  *              Region 1 Base Address .
00716  *  @param  region1Size
00717  *              Region 1 Size .
00718  *  @param  region2Addr
00719  *              Region 2 Base Address .
00720  *  @param  region2Size
00721  *              Region 2 Size .
00722  *  @param  region3Addr
00723  *              Region 3 Base Address .
00724  *  @param  region3Size
00725  *              Region 3 Size .
00726  *  @param  region4Addr
00727  *              Region 4 Base Address .
00728  *  @param  region4Size
00729  *              Region 4 Size .
00730  *  @param  prevUserAddr
00731  *              Stores previous page base address .
00732  *  @param  prevUserSize
00733  *              Stores previous page size .
00734  *  @param  ctrlBaseAddr
00735  *              Base Address of VLYNQ Control.
00736  *  @param  intVector
00737  *              Vlynq interrupt vector number.
00738  *  @param  edmaChnlId
00739  *              Edma channel number.
00740  *  ============================================================================
00741  */
00742 struct DM6437_HalVlynqPhyObj_tag {
00743     Uint32 region1Addr   ;
00744     Uint32 region1Size   ;
00745     Uint32 region2Addr   ;
00746     Uint32 region2Size   ;
00747     Uint32 region3Addr   ;
00748     Uint32 region3Size   ;
00749     Uint32 region4Addr   ;
00750     Uint32 region4Size   ;
00751     Uint32 prevUserAddr  ;
00752     Uint32 prevUserSize  ;
00753     Uint32 ctrlBaseAddr  ;
00754     Uint8  intVector     ;
00755     Uint32 edmaChnlId    ;
00756 } ;
00757 
00758 
00759 #if defined (__cplusplus)
00760 }
00761 #endif /* if defined (__cplusplus) */
00762 
00763 #endif /* !defined (DM6437_HAL_VLYNQ_H) */

Generated on Fri Jul 16 14:34:01 2010 for DSP/BIOSLink by  doxygen 1.4.4