Data Sheet for the DSP server image

Server DSP image name bin/ti_platforms_evm3530/audio1_ires.x64P
BIOS-related Configuration
defaultMemSegIdDDR2
enableLoggingtrue
traceBufferSize0x00008000
logNameti_sdo_ce_osal_LOG_Buffer
logSize0x00000100
logTypecircular
logSegDDR2
Server Algorithms
Codec name (alias)auddec1_ires
Codec typeXDM audio decoder (ti.sdo.ce.audio1.IAUDDEC1)
Packageti.sdo.ce.examples.codecs.auddec1_ires
ModuleAUDDEC1_IRES
Codec package location at server build time/db/atree/library/trees/ce/ce-r09x/src/
Package version[ 1, 0, 0 ]
RPC protocol version 1
Thread attributes
Priority
2
Stack Size
default for the alg (1024 bytes) + 8192 bytes padding

Group ID number 0 (auto-assigned value)

Codec name (alias)audenc1_copy
Codec typeXDM audio encoder (ti.sdo.ce.audio1.IAUDENC1)
Packageti.sdo.ce.examples.codecs.audenc1_copy
ModuleAUDENC1_COPY
Codec package location at server build time/db/atree/library/trees/ce/ce-r09x/src/
Package version[ 1, 0, 0 ]
RPC protocol version 1
Thread attributes
Priority
2
Stack Size
default for the alg (1024 bytes) + 8192 bytes padding

Group ID number 0 (auto-assigned value)
Server DMA (DMAN3)
config
MAXGROUPS0x00000014
heapInternalL1DHEAP
heapExternalDDR2
scratchAllocFxnundefined
scratchFreeFxnundefined
idma3Internaltrue
cpufalse
useExternalRMfalse
numQdmaChannels0x00000004
qdmaPaRamBase0x01C04000
maxPaRamEntries0x00000080
maxQdmaChannels0x00000008
maxTCs0x00000008
paRamBaseIndex0x00000060
numPaRamEntries0x00000020
nullPaRamIndex0x00000000
qdmaChannels[ 0, 1, 2, 3 ]
tccAllocationMaskH0xFFFFFFFF
tccAllocationMaskL0x00000000
qdmaQueueMap[ 1, 1, 1, 1, 1, 1, 1, 1 ]
queueTCMap[ 0, 1, 2, 3, 4, 5, 6, 7 ]
queuePri[ 3, 7, 0, 0, 0, 0, 0, 0 ]
numTccGroup[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
numPaRamGroup[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
ipcKeyBase0x4E414D44
allowUnsharedtrue
Algorithm memory
allocation (DSKT2)
config
DEFAULTSEGIRAM
DARAM0L1DHEAP
DARAM1L1DHEAP
DARAM2L1DHEAP
SARAM0L1DHEAP
SARAM1L1DHEAP
SARAM2L1DHEAP
ESDATADDRALGHEAP
IPROGL1DHEAP
EPROGDDRALGHEAP
DSKT2_HEAPDDR2
ALLOW_EXTERNAL_SCRATCHtrue
DARAM_SCRATCH_SIZES[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
SARAM_SCRATCH_SIZES[ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
cacheWritebackInvalidateFxnBCACHE_wbInv
DSP memory map
NameMEM_NULL
Base0x00000000
Len0x00000000
DescriptionPlace holder segment which allows user to disable heaps

NameCACHE_L1D
Base0x10F10000
Len0x00008000
DescriptionDo not delete, in use by cache

NameL4PER
Base0x49000000
Len0x00100000
DescriptionL4PER: L4-Peripheral Interconnect Address Space

NameDDR2
Base0x87800000
Len0x00600000
DescriptionDDR2: off-chip memory for application code and data

NameBUFMEM
Base0x10F0FB00
Len0x00000500
Description

NameIRAM
Base0x107F8000
Len0x00008000
DescriptionInternal 96K L2 RAM/CACHE in UMAP0

NameCACHE_L2
Base0x10800000
Len0x00010000
DescriptionDo not delete, in use by cache

NameL1DSRAM
Base0x10F04000
Len0x0000BB00
DescriptionInternal 80K RAM/CACHE L1 Data Memory in Region 0

NameCACHE_L1P
Base0x10E00000
Len0x00008000
DescriptionDo not delete, in use by cache

NameRESET_VECTOR
Base0x87F00000
Len0x00001000
DescriptionRESET_VECTOR: off-chip memory for the reset vector table

NameDDRALGHEAP
Base0x86000000
Len0x01800000
DescriptionDDRALGHEAP: off-chip memory for dynamic algmem allocation

NameL4CORE
Base0x48000000
Len0x01000000
DescriptionL4CORE: L4-Core Interconnect Address Space

NameDSPLINKMEM
Base0x87E00000
Len0x00100000
DescriptionDSPLINK: off-chip memory reserved for DSPLINK code and data

NameCMEM
Base<to be set to CMEM block address at server load time>
Len<to be set to CMEM block size at server load time>
Descriptionplaceholder for the CMEM segment that the Arm side creates for I/O buffer exchange with the DSP; on OMAP devices the CMEM segment is automatically mapped on the DSP at DSP server load time so the DSP can access the Arm I/O buffers
Misc settings
Server thread priority1
Server thread stack size2048 bytes
autoGenScratchSizeArraystrue
Skeleton Caching PolicyLOCALBUFFERINVWB (default)
Configured DSP clock speed 330 MHz (set in the GBL.CLKOUT TCF field; may or may not match the actual DSP clock speed)
Configuration example Add the following code to your Arm-side application configuration file (.cfg) to create an Engine from this server:
var Engine = xdc.useModule('ti.sdo.ce.Engine');
var myEngine = Engine.createFromServer(
    "bin/ti_platforms_evm3530/audio1_ires",  // Engine name (as referred to in the C app)
    "bin/ti_platforms_evm3530/audio1_ires.x64P", // path to server exe, relative to its package dir
    "ti.sdo.ce.examples.servers.audio1_ires" // full server package name
);