1    /* 
     2     * Copyright (c) 2010, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     * 
    32     */
    33    
    34    /*!
    35     *  ======== DspLinkCfg ========
    36     *  Dsplink ipc Settings.
    37     */
    38    
    39    metaonly module DspLinkCfg inherits ti.sdo.ce.ipc.dsplink.IDspLinkCfg {
    40    
    41      /*
    42       * The DEFAULT_ARMDSPLINKCONFIG[] table is here mostly for backward
    43       * compatibility purposes.  The current recommended approach for creating
    44       * an 'ArmDspLinkConfig' is to simply use Engine.createFromServer(), which
    45       * creates and populates an 'ArmDspLinkConfig' object based on the server's
    46       * memory map for 'memTable' and default values for other fields.
    47       *
    48       * When Engine.createFromServer() is used, this table becomes unused.
    49       */
    50      override readonly config ti.sdo.ce.ipc.IIpc.ArmDspLinkConfig
    51            DEFAULT_ARMDSPLINKCONFIG[string] = [
    52    
    53        /* DM6446, 256 MB of external memory */
    54        ["TMS320CDM6446",
    55        {
    56            memTable: [
    57               ["DDRALGHEAP", {addr: 0x88000000, size: 0x07A00000, type: "other"}],
    58               ["DDR2",       {addr: 0x8FA00000, size: 0x00400000, type: "main" }],
    59               ["DSPLINKMEM", {addr: 0x8FE00000, size: 0x00100000, type: "link" }],
    60               ["RESETCTRL",  {addr: 0x8FF00000, size: 0x00000080, type: "reset"}],
    61            ],
    62            doPowerControl : false,
    63            dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
    64        }],
    65    
    66        /* DM357, 256 MB of external memory */
    67        ["TMS320DM357",
    68        {
    69            memTable: [
    70               ["DDRALGHEAP", {addr: 0x88000000, size: 0x07A00000, type: "other"}],
    71               ["DDR2",       {addr: 0x8FA00000, size: 0x00400000, type: "main" }],
    72               ["DSPLINKMEM", {addr: 0x8FE00000, size: 0x00100000, type: "link" }],
    73               ["RESETCTRL",  {addr: 0x8FF00000, size: 0x00000080, type: "reset"}],
    74            ],
    75            doPowerControl : false,
    76            dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
    77        }],
    78    
    79        /* DM6467, 256 MB of external memory */
    80        ["TMS320CDM6467",
    81        {
    82            memTable: [
    83               ["DDRALGHEAP", {addr: 0x88000000, size: 0x07A00000, type: "other"}],
    84               ["DDR2",       {addr: 0x8FA00000, size: 0x00400000, type: "main" }],
    85               ["DSPLINKMEM", {addr: 0x8FE00000, size: 0x00100000, type: "link" }],
    86               ["RESETCTRL",  {addr: 0x8FF00000, size: 0x00000080, type: "reset"}],
    87            ],
    88            doPowerControl : false,
    89            dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
    90        }],
    91    
    92        /* OMAP3430, 128 MB of external memory */
    93        ["TMS320C3430",
    94        {
    95            memTable: [
    96                ["L4CORE",     {addr: 0x48000000, size: 0x01000000, type: "other"}],
    97                ["L4PER",      {addr: 0x49000000, size: 0x00100000, type: "other"}],
    98                ["CMEM",       {addr: 0x85000000, size: 0x01000000, type: "other"}],
    99                ["DDRALGHEAP", {addr: 0x86000000, size: 0x01800000, type: "other"}],
   100                ["DDR2",       {addr: 0x87800000, size: 0x00600000, type: "main" }],
   101                ["DSPLINKMEM", {addr: 0x87E00000, size: 0x00100000, type: "link" }],
   102                ["RESETCTRL",  {addr: 0x87F00000, size: 0x00001000, type: "reset"}],
   103            ],
   104            doPowerControl : false,
   105            dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
   106        }],
   107    
   108        /* OMAP3530, 128 MB of external memory */
   109        ["OMAP3530",
   110        {
   111            memTable: [
   112                ["L4CORE",     {addr: 0x48000000, size: 0x01000000, type: "other"}],
   113                ["L4PER",      {addr: 0x49000000, size: 0x00100000, type: "other"}],
   114                ["CMEM",       {addr: 0x85000000, size: 0x01000000, type: "other"}],
   115                ["DDRALGHEAP", {addr: 0x86000000, size: 0x01800000, type: "other"}],
   116                ["DDR2",       {addr: 0x87800000, size: 0x00600000, type: "main" }],
   117                ["DSPLINKMEM", {addr: 0x87E00000, size: 0x00100000, type: "link" }],
   118                ["RESETCTRL",  {addr: 0x87F00000, size: 0x00001000, type: "reset"}],
   119            ],
   120            doPowerControl : false,
   121            dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
   122        }],
   123    
   124        /* OMAP2530, 64 MB of external memory */
   125        ["OMAP2530",
   126        {
   127            memTable: [
   128                ["L4CORE",     {addr: 0x48000000, size: 0x01000000, type: "other"}],
   129                ["L4WAKEUP",   {addr: 0x49000000, size: 0x00800000, type: "other"}],
   130                ["CMEM",       {addr: 0x82400000, size: 0x00800000, type: "other"}],
   131                ["DDR2",       {addr: 0x82C00000, size: 0x00300000, type: "main" }],
   132                ["DSPLINKMEM", {addr: 0x82F00000, size: 0x000FF000, type: "link" }],
   133                ["RESETCTRL",  {addr: 0x82FFF000, size: 0x00001000, type: "reset"}],
   134                ["DDRALGHEAP", {addr: 0x83000000, size: 0x01000000, type: "other"}],
   135            ],
   136            doPowerControl : false,
   137            dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
   138        }],
   139    
   140        /* TMS320C2430, 128 MB of external memory */
   141        ["TMS320C2430",
   142        {
   143            memTable: [
   144                ["L4CORE",     {addr: 0x48000000, size: 0x01000000, type: "other"}],
   145                ["L4WAKEUP",   {addr: 0x49000000, size: 0x00800000, type: "other"}],
   146                ["CMEM",       {addr: 0x85800000, size: 0x00800000, type: "other"}],
   147                ["DDRALGHEAP", {addr: 0x86000000, size: 0x01800000, type: "other"}],
   148                ["DDR2",       {addr: 0x87800000, size: 0x00600000, type: "main" }],
   149                ["DSPLINKMEM", {addr: 0x87E00000, size: 0x00100000, type: "link" }],
   150                ["RESETCTRL",  {addr: 0x87F00000, size: 0x00001000, type: "reset"}],
   151            ],
   152            doPowerControl : false,
   153            dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
   154        }],
   155    
   156        /* OMAPL137, 64 MB of external memory */
   157        ["OMAPL137",
   158        {
   159            memTable: [
   160               ["DDRALGHEAP", {addr: 0xC3000000, size: 0x01000000, type: "other"}],
   161               ["DDR2",       {addr: 0xC2C00000, size: 0x00300000, type: "main" }],
   162               ["DSPLINKMEM", {addr: 0xC2F01000, size: 0x00100000, type: "link" }],
   163               ["RESETCTRL",  {addr: 0xC2F00000, size: 0x00001000, type: "reset"}],
   164            ],
   165            doPowerControl : true,
   166            dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
   167        }],
   168    
   169        /* OMAPL138, 64 MB of external memory */
   170        ["OMAPL138",
   171        {
   172            memTable: [
   173               ["DDRALGHEAP", {addr: 0xC3000000, size: 0x01000000, type: "other"}],
   174               ["DDR2",       {addr: 0xC2C00000, size: 0x00300000, type: "main" }],
   175               ["DSPLINKMEM", {addr: 0xC2F01000, size: 0x00100000, type: "link" }],
   176               ["RESETCTRL",  {addr: 0xC2F00000, size: 0x00001000, type: "reset"}],
   177            ],
   178            doPowerControl : true,
   179            dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
   180        }],
   181    
   182        ];
   183    }
   184    /*
   185     *  @(#) ti.sdo.ce.ipc.dsplink; 2, 0, 1,179; 9-20-2010 16:41:35; /db/atree/library/trees/ce/ce-r09x/src/ xlibrary
   186    
   187     */
   188