1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
33
34 /*!
35 * ======== DspLinkCfg ========
36 * Dsplink ipc Settings.
37 */
38
39 metaonly module DspLinkCfg inherits ti.sdo.ce.ipc.dsplink.IDspLinkCfg {
40
41 42 43 44 45 46 47 48 49
50 override readonly config ti.sdo.ce.ipc.IIpc.ArmDspLinkConfig
51 DEFAULT_ARMDSPLINKCONFIG[string] = [
52
53
54 ["TMS320CDM6446",
55 {
56 memTable: [
57 ["DDRALGHEAP", {addr: 0x88000000, size: 0x07A00000, type: "other"}],
58 ["DDR2", {addr: 0x8FA00000, size: 0x00400000, type: "main" }],
59 ["DSPLINKMEM", {addr: 0x8FE00000, size: 0x00100000, type: "link" }],
60 ["RESETCTRL", {addr: 0x8FF00000, size: 0x00000080, type: "reset"}],
61 ],
62 doPowerControl : false,
63 dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
64 }],
65
66
67 ["TMS320DM357",
68 {
69 memTable: [
70 ["DDRALGHEAP", {addr: 0x88000000, size: 0x07A00000, type: "other"}],
71 ["DDR2", {addr: 0x8FA00000, size: 0x00400000, type: "main" }],
72 ["DSPLINKMEM", {addr: 0x8FE00000, size: 0x00100000, type: "link" }],
73 ["RESETCTRL", {addr: 0x8FF00000, size: 0x00000080, type: "reset"}],
74 ],
75 doPowerControl : false,
76 dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
77 }],
78
79
80 ["TMS320CDM6467",
81 {
82 memTable: [
83 ["DDRALGHEAP", {addr: 0x88000000, size: 0x07A00000, type: "other"}],
84 ["DDR2", {addr: 0x8FA00000, size: 0x00400000, type: "main" }],
85 ["DSPLINKMEM", {addr: 0x8FE00000, size: 0x00100000, type: "link" }],
86 ["RESETCTRL", {addr: 0x8FF00000, size: 0x00000080, type: "reset"}],
87 ],
88 doPowerControl : false,
89 dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
90 }],
91
92
93 ["TMS320C3430",
94 {
95 memTable: [
96 ["L4CORE", {addr: 0x48000000, size: 0x01000000, type: "other"}],
97 ["L4PER", {addr: 0x49000000, size: 0x00100000, type: "other"}],
98 ["CMEM", {addr: 0x85000000, size: 0x01000000, type: "other"}],
99 ["DDRALGHEAP", {addr: 0x86000000, size: 0x01800000, type: "other"}],
100 ["DDR2", {addr: 0x87800000, size: 0x00600000, type: "main" }],
101 ["DSPLINKMEM", {addr: 0x87E00000, size: 0x00100000, type: "link" }],
102 ["RESETCTRL", {addr: 0x87F00000, size: 0x00001000, type: "reset"}],
103 ],
104 doPowerControl : false,
105 dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
106 }],
107
108
109 ["OMAP3530",
110 {
111 memTable: [
112 ["L4CORE", {addr: 0x48000000, size: 0x01000000, type: "other"}],
113 ["L4PER", {addr: 0x49000000, size: 0x00100000, type: "other"}],
114 ["CMEM", {addr: 0x85000000, size: 0x01000000, type: "other"}],
115 ["DDRALGHEAP", {addr: 0x86000000, size: 0x01800000, type: "other"}],
116 ["DDR2", {addr: 0x87800000, size: 0x00600000, type: "main" }],
117 ["DSPLINKMEM", {addr: 0x87E00000, size: 0x00100000, type: "link" }],
118 ["RESETCTRL", {addr: 0x87F00000, size: 0x00001000, type: "reset"}],
119 ],
120 doPowerControl : false,
121 dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
122 }],
123
124
125 ["OMAP2530",
126 {
127 memTable: [
128 ["L4CORE", {addr: 0x48000000, size: 0x01000000, type: "other"}],
129 ["L4WAKEUP", {addr: 0x49000000, size: 0x00800000, type: "other"}],
130 ["CMEM", {addr: 0x82400000, size: 0x00800000, type: "other"}],
131 ["DDR2", {addr: 0x82C00000, size: 0x00300000, type: "main" }],
132 ["DSPLINKMEM", {addr: 0x82F00000, size: 0x000FF000, type: "link" }],
133 ["RESETCTRL", {addr: 0x82FFF000, size: 0x00001000, type: "reset"}],
134 ["DDRALGHEAP", {addr: 0x83000000, size: 0x01000000, type: "other"}],
135 ],
136 doPowerControl : false,
137 dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
138 }],
139
140
141 ["TMS320C2430",
142 {
143 memTable: [
144 ["L4CORE", {addr: 0x48000000, size: 0x01000000, type: "other"}],
145 ["L4WAKEUP", {addr: 0x49000000, size: 0x00800000, type: "other"}],
146 ["CMEM", {addr: 0x85800000, size: 0x00800000, type: "other"}],
147 ["DDRALGHEAP", {addr: 0x86000000, size: 0x01800000, type: "other"}],
148 ["DDR2", {addr: 0x87800000, size: 0x00600000, type: "main" }],
149 ["DSPLINKMEM", {addr: 0x87E00000, size: 0x00100000, type: "link" }],
150 ["RESETCTRL", {addr: 0x87F00000, size: 0x00001000, type: "reset"}],
151 ],
152 doPowerControl : false,
153 dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
154 }],
155
156
157 ["OMAPL137",
158 {
159 memTable: [
160 ["DDRALGHEAP", {addr: 0xC3000000, size: 0x01000000, type: "other"}],
161 ["DDR2", {addr: 0xC2C00000, size: 0x00300000, type: "main" }],
162 ["DSPLINKMEM", {addr: 0xC2F01000, size: 0x00100000, type: "link" }],
163 ["RESETCTRL", {addr: 0xC2F00000, size: 0x00001000, type: "reset"}],
164 ],
165 doPowerControl : true,
166 dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
167 }],
168
169
170 ["OMAPL138",
171 {
172 memTable: [
173 ["DDRALGHEAP", {addr: 0xC3000000, size: 0x01000000, type: "other"}],
174 ["DDR2", {addr: 0xC2C00000, size: 0x00300000, type: "main" }],
175 ["DSPLINKMEM", {addr: 0xC2F01000, size: 0x00100000, type: "link" }],
176 ["RESETCTRL", {addr: 0xC2F00000, size: 0x00001000, type: "reset"}],
177 ],
178 doPowerControl : true,
179 dspManagement : ti.sdo.ce.ipc.IIpc.BootAndLoadDsp
180 }],
181
182 ];
183 }
184 185 186 187
188