Server DSP image name |
bin/ti_platforms_evmOMAPL138/audio1_ires.x674 |
BIOS-related Configuration |
defaultMemSegId | SDRAM |
enableLogging | true |
traceBufferSize | 0x00008000 |
logName | ti_sdo_ce_osal_LOG_Buffer |
logSize | 0x00000100 |
logType | circular |
logSeg | SDRAM |
|
Server Algorithms |
Codec name (alias) | auddec1_ires |
Codec type | XDM audio decoder (ti.sdo.ce.audio1.IAUDDEC1) |
Package | ti.sdo.ce.examples.codecs.auddec1_ires |
Module | AUDDEC1_IRES |
Codec package location at server build time | /db/atree/library/trees/ce/ce-r09x/src/ |
Package version | [ 1, 0, 0 ] |
RPC protocol version |
1
|
Thread attributes |
Priority
|
2
|
Stack Size
|
default for the alg (1024 bytes) + 8192 bytes padding
|
|
Group ID number |
0 (auto-assigned value)
|
Codec name (alias) | audenc1_copy |
Codec type | XDM audio encoder (ti.sdo.ce.audio1.IAUDENC1) |
Package | ti.sdo.ce.examples.codecs.audenc1_copy |
Module | AUDENC1_COPY |
Codec package location at server build time | /db/atree/library/trees/ce/ce-r09x/src/ |
Package version | [ 1, 0, 0 ] |
RPC protocol version |
1
|
Thread attributes |
Priority
|
2
|
Stack Size
|
default for the alg (1024 bytes) + 8192 bytes padding
|
|
Group ID number |
0 (auto-assigned value)
|
|
Server DMA (DMAN3) config |
MAXGROUPS | 0x00000014 |
heapInternal | L1DHEAP |
heapExternal | SDRAM |
scratchAllocFxn | undefined |
scratchFreeFxn | undefined |
idma3Internal | true |
cpu | false |
useExternalRM | false |
numQdmaChannels | 0x00000004 |
qdmaPaRamBase | 0x01C04000 |
maxPaRamEntries | 0x00000080 |
maxQdmaChannels | 0x00000008 |
maxTCs | 0x00000008 |
paRamBaseIndex | 0x00000060 |
numPaRamEntries | 0x00000020 |
nullPaRamIndex | 0x00000000 |
qdmaChannels | [ 0, 1, 2, 3 ] |
tccAllocationMaskH | 0x00000000 |
tccAllocationMaskL | 0xFFFFFFFF |
qdmaQueueMap | [ 1, 1, 1, 1, 1, 1, 1, 1 ] |
queueTCMap | [ 0, 1, 2, 3, 4, 5, 6, 7 ] |
queuePri | [ 3, 7, 0, 0, 0, 0, 0, 0 ] |
numTccGroup | [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] |
numPaRamGroup | [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] |
ipcKeyBase | 0x4E414D44 |
allowUnshared | true |
|
Algorithm memory allocation (DSKT2) config |
DEFAULTSEG | IRAM |
DARAM0 | L1DHEAP |
DARAM1 | L1DHEAP |
DARAM2 | L1DHEAP |
SARAM0 | L1DHEAP |
SARAM1 | L1DHEAP |
SARAM2 | L1DHEAP |
ESDATA | DDRALGHEAP |
IPROG | L1DHEAP |
EPROG | DDRALGHEAP |
DSKT2_HEAP | SDRAM |
ALLOW_EXTERNAL_SCRATCH | true |
DARAM_SCRATCH_SIZES | [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] |
SARAM_SCRATCH_SIZES | [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] |
cacheWritebackInvalidateFxn | BCACHE_wbInv |
|
DSP memory map |
Name | MEM_NULL |
Base | 0x00000000 |
Len | 0x00000000 |
Description | Place holder segment which allows user to disable heaps |
Name | CACHE_L1D |
Base | 0x11F04000 |
Len | 0x00004000 |
Description | Do not delete, in use by cache |
Name | BUFMEM |
Base | 0x11F03B00 |
Len | 0x00000500 |
Description | |
Name | IRAM |
Base | 0x11800000 |
Len | 0x00020000 |
Description | Internal 256K L2 RAM/CACHE |
Name | SDRAM |
Base | 0xC2C00000 |
Len | 0x00300000 |
Description | SDRAM: off-chip memory for application code and data |
Name | CACHE_L2 |
Base | 0x11820000 |
Len | 0x00020000 |
Description | Do not delete, in use by cache |
Name | L1DSRAM |
Base | 0x11F00000 |
Len | 0x00003B00 |
Description | Internal 32K RAM/CACHE L1 Data Memory |
Name | L3_CBA_RAM |
Base | 0x80000000 |
Len | 0x00020000 |
Description | 128KB ARM/DSP local shared RAM |
Name | CACHE_L1P |
Base | 0x11E00000 |
Len | 0x00008000 |
Description | Do not delete, in use by cache |
Name | RESET_VECTOR |
Base | 0xC2F00000 |
Len | 0x00001000 |
Description | RESET_VECTOR: off-chip memory for the reset vector table |
Name | DDRALGHEAP |
Base | 0xC3000000 |
Len | 0x01000000 |
Description | DDRALGHEAP: off-chip memory for dynamic algmem allocation |
Name | DSPLINKMEM |
Base | 0xC2F01000 |
Len | 0x000FF000 |
Description | DSPLINK: off-chip memory reserved for DSPLINK code and data |
|
Misc settings |
Server thread priority | 1 |
Server thread stack size | 2048 bytes |
autoGenScratchSizeArrays | true |
Skeleton Caching Policy | LOCALBUFFERINVWB (default) |
|
Configured DSP clock speed |
300 MHz (set in the GBL.CLKOUT TCF field; may or may not match the actual DSP clock speed) |
Configuration example |
Add the following code to your Arm-side application configuration file (.cfg) to create an Engine from this server:
var Engine = xdc.useModule('ti.sdo.ce.Engine');
var myEngine = Engine.createFromServer(
"bin/ti_platforms_evmOMAPL138/audio1_ires", // Engine name (as referred to in the C app)
"bin/ti_platforms_evmOMAPL138/audio1_ires.x674", // path to server exe, relative to its package dir
"ti.sdo.ce.examples.servers.audio1_ires" // full server package name
);
|