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33 /*!
34 * ======== DMAN3 ========
35 * EDMA3 QDMA resource manager.
36 */
37 @Template("./DMAN3.xdt")
38
39 metaonly module DMAN3 {
40
41
42
43 /*!
44 * ======== heapInternal ========
45 * Heap ID for dynamic allocation of DMAN3 objects.
46 *
47 * This must be allocated in L1D Internal RAM.
48 *
49 * This parameter is unused when DMAN3 is used in a Linux environment.
50 *
51 * This parameter is set to `DMAN3_HEAP_INTERNAL`.
52 */
53 config String heapInternal = "DMAN3_heapInternal_undefined";
54
55 /*!
56 * ======== heapExternal ========
57 * Heap ID for dyn allocation of private DMAN3 data structures.
58 *
59 * This parameter is unused when DMAN3 is used in a Linux environment.
60 *
61 * This parameter is set to `DMAN3_HEAP_EXTERNAL`.
62 */
63 config String heapExternal = "DMAN3_heapExternal_undefined";
64
65 /*!
66 * ======== scratchAllocFxn ========
67 * Function for allocating IDMA3 channel object's "env" in scratch
68 * memory.
69 */
70 config String scratchAllocFxn = null;
71
72 /*!
73 * ======== scratchFreeFxn ========
74 * Function for freeing IDMA3 channel object's "env" that was allocated
75 * in scratch memory.
76 */
77 config String scratchFreeFxn = null;
78
79 /*!
80 * ======== idma3Internal ========
81 * Use the internal memory heap for dynamic allocation of IDMA3 objects.
82 *
83 * A value of `false` means that IDMA3 objects will be allocated
84 * in the heap specified by {@link #heapExternal}. If the
85 * value is `true`, IDMA3 objects will be
86 * allocated in the heap specified by {@link #heapInternal}.
87 */
88 config bool idma3Internal = true;
89
90 /*!
91 * ======== cpu ========
92 * Use the non-EDMA3, CPU version of DMAN3.
93 */
94 config bool cpu = false;
95
96 /*!
97 * ======= useExternalRM =======
98 * Boolean flag indicating if the EDMA3 Low Level
99 * Resource Manager should be used to manage EDMA3
100 * resources. If this flag is set to true, the SOC
101 * specific settings are not required to be set in
102 * this module. The ti.sdo.fc.edma3.Settings module
103 * should be set up correctly
104 */
105 config bool useExternalRM = false;
106
107 /*!
108 * ======== numQdmaChannels ========
109 * The number of Physical QDMA channels that are assigned to
110 * DMAN3 via configuration. These channels will be granted either
111 * as scratch or persistently as part of IDMA3 handles.
112 *
113 * This parameter is set to `DMAN3_NUM_QDMA_CHANNELS`.
114 */
115 config UInt numQdmaChannels = 4;
116
117 118 119
120
121
122 /*!
123 * ======== qdmaPaRamBase ========
124 * Physical base address of the PARAM0 in the EDMA3/QDMA
125 * hardware whose resources are being managed by DMAN3.
126 *
127 * This parameter is set to `DMAN3_QDMA_PARAM_BASE`.
128 */
129 config Ptr qdmaPaRamBase = 0x01C04000;
130
131 /*!
132 * ======== maxPaRamEntries ========
133 * Total number of PARAM Table entries on the target hardware.
134 * (eg, for IVA2, Davinci this is 128, for Himalaya, this is 256).
135 *
136 * This parameter is set to `DMAN3_MAX_PARAM_ENTRIES`.
137 */
138 config UInt maxPaRamEntries = 128;
139
140 /*!
141 * ======== maxQdmaChannels ========
142 * The total number of Physical QDMA channels available on the
143 * target hardware (eg, 8 for DaVinci, 4 for IVA2).
144 *
145 * This parameter is set to `DMAN3_MAX_QDMA_CHANNELS`.
146 */
147 config UInt maxQdmaChannels = 8;
148
149 /*!
150 * ======= maxTCs ========
151 * Maximum number of transfer controllers on this SOC
152 */
153 config UInt maxTCs = 8;
154
155
156 157 158 159
160
161 /*!
162 * ======== paRamBaseIndex ========
163 * (0 > value > 255) represents the first PARAM TABLE ENTRY
164 * NUMBER that is assigned by configuration for exclusive DMAN3 allocation.
165 *
166 * Typically, addresses (PaRam sets) between 0 and 63 are reserved for use
167 * by drivers that need EDMA/chaining capabilities.
168 *
169 * Additionally, on some multi-core devices (e.g. DM644x), PaRams are
170 * shared between the different cores (e.g. ARM and C64+). In these
171 * cases, an executable will be configured for each core, and each
172 * executable should configure only the DMAN3 resources which will be used
173 * on that core. E.g., on DM644x, the C64+ executable should
174 * be configured to avoid using what the ARM uses. Note that on
175 * OMAP2430, the ARM doesn't have access to EDMA so all PaRam sets
176 * are available for the C64+ device.
177 *
178 * This parameter is set to `DMAN3_PARAM_BASE_INDEX`.
179 */
180 config UInt paRamBaseIndex = 96;
181
182 /*!
183 * ======== numPaRamEntries ========
184 * Number of PARAM Table entries starting at DMAN3_PARAM_BASE_INDEX
185 * assigned by configuration for exclusive DMAN3 allocation.
186 *
187 * This parameter is set to `DMAN3_NUM_CONTIGUOUS_PARAM_ENTRIES`.
188 */
189 config UInt numPaRamEntries = 32;
190
191 /*!
192 * ======== nullPaRamIndex ========
193 * Index of PARAM to be reserved as a "null" PaRam. This index will be
194 * used to set QCHMAP when the corresponding QDMA channel is not active.
195 * The value of nullPaRamIndex should be outside of the range of
196 * PaRam indices alloted to DMAN3, i.e., nullPaRamIndex should be less
197 * than paRamBaseIndex, or greater than paRamBaseIndex + numPaRamEntries.
198 * If PaRam registers are shared between two processors (eg, an Arm
199 * and a DSP), make sure the nullPaRamIndex is not used by the other
200 * processor.
201 *
202 * This parameter is set to `DMAN3_NULLPARAMINDEX`.
203 */
204 config UInt nullPaRamIndex = 0;
205
206 /*!
207 * ======== qdmaChannels ========
208 * Array containing list of physical QDMA channels assigned to DMAN3.
209 *
210 * This array is of size `DMAN3_NUM_QDMA_CHANNELS`
211 * (configured by {@link #numQdmaChannels}).
212 *
213 * This parameter is set to `DMAN3_QDMA_CHANNELS[]`.
214 *
215 * @see numQdmaChannels
216 */
217 config UInt qdmaChannels[] = [0, 1, 2, 3];
218
219 /*!
220 * ======== tccAllocationMaskH ========
221 * 32-bit bitmask representing configuration provided list of TCCs
222 * for exclusive DMAN3 allocation.
223 *
224 * For example, for TCC's in the range 0-31 the Low Mask
225 * (tccAllocationMaskL) is configured so that a '1' in bit position 'i'
226 * indicates the TCC 'i' is assigned to DMAN3.
227 *
228 * This parameter is set to `DMAN3_TCC_FREEMASK_H`.
229 */
230 config UInt tccAllocationMaskH = 0xffffffff;
231
232 /*!
233 * ======== tccAllocationMaskL ========
234 * 32-bit bitmask representing configuration provided list of TCCs
235 * for exclusive DMAN3 allocation.
236 *
237 * For example, for TCC's in the range 0-31 the Low Mask
238 * (tccAllocationMaskL) is configured so that a '1' in bit position 'i'
239 * indicates the TCC 'i' is assigned to DMAN3.
240 *
241 * This parameter is set to `DMAN3_TCC_FREEMASK_L`.
242 */
243 config UInt tccAllocationMaskL = 0x00000000;
244
245 /*!
246 * ======= qdmaQueueMap ========
247 * Array contaning the mapping from QDMA Channels to Event Queues
248 *
249 * Indicates mapping of all "qdmaChannels" defined above to
250 * particular Event Queue. For example, `channelQueueMap[0]`
251 * specifies queue number for `qdmaChannel[0]`, etc.
252 *
253 * Defaults map all qdmaChannels to Queue# 1
254 */
255 config UInt qdmaQueueMap[] = [1,1,1,1,1,1,1,1];
256
257 /*!
258 * ======= queueTCMap ========
259 * Array contaning the mapping from Event Queues to Transfer Controllers
260 *
261 * Indicates mapping of individual hardware Event Queues to the Transfer
262 * Controllers.
263 */
264 config UInt queueTCMap[] = [0, 1, 2, 3, 4, 5, 6, 7];
265
266 /*!
267 * ======= queuePri ========
268 * Array contaning priorities of the event queues
269 *
270 * Indicates the priority accorded to each physical event queue.
271 */
272 config UInt queuePri[] = [3, 7, 0, 0, 0, 0, 0, 0];
273
274
275
276 const Int MAXGROUPS = 20; /*! Maximum number of groups for sharing
277 TCCs and parameter RAM. */
278
279
280
281 /*!
282 * ======== numTccGroup ========
283 * Arrays containing the number of TCC that will be assigned to groups for
284 * sharing
285 *
286 * Channels created with a given group ID will use TCCs and PaRams
287 * allocated for that group ID, and may share them with other channels
288 * created with the same group ID.
289 *
290 * This parameter is set to `DMAN3_NUMTCC_GROUP`.
291 */
292 config Int numTccGroup[MAXGROUPS] = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0, 0, 0,
293 0, 0, 0, 0, 0, 0, 0,];
294
295 /*!
296 * ======== numPaRamGroup ========
297 * Arrays containing the number of PaRam entries that will be assigned to
298 * groups for sharing.
299 *
300 * Channels created with a given group ID will use TCCs and PaRams
301 * allocated for that group ID, and may share them with other channels
302 * created with the same group ID.
303 *
304 * This parameter is set to `DMAN3_NUMPARAM_GROUP`.
305 */
306 config Int numPaRamGroup[MAXGROUPS]= [0, 0, 0, 0, 0, 0, 0, 0, 0, 0,0, 0, 0,
307 0, 0, 0, 0, 0, 0, 0,] ;
308
309 310 311 312
313
314 /*!
315 * ======== debug ========
316 * Enable the debug profile of the DMAN3 library.
317 *
318 * This will likely result in a larger and slower library being linked in.
319 */
320 config bool debug = false;
321
322 /*!
323 * ======== trace ========
324 * Enable trace support
325 */
326 config bool trace = false;
327
328 /*!
329 * ======== ipcKeyBase ========
330 * Linux only. Base value of keys of Linux IPC objects used by
331 * DMAN3. The IPC objects created by DMAN3 will use keys starting at this
332 * value, and incrementing with each new object. There are currently
333 * three IPC objects, so keys in the range of ipcKeyBase to ipcKeyBase + 2
334 * will be reserved for DMAN3. The default value of ipcKeyBase is
335 * ascii code for "NAMD".
336 *
337 * WARNING: This value should only be changed if it conflicts with
338 * another IPC key in the system that cannot be changed. If this value
339 * is changed, all programs using DMAN3 that will be run simultaneously
340 * must have the ipcKeyBase configured to the new value.
341 * @_nodoc
342 */
343 config UInt ipcKeyBase = 0x4e414d44;
344
345 /*!
346 * ======== allowUnshared ========
347 * Allow DMAN3-related resources to be granted to an algorithm, even
348 * if there are not enough resources configured into the shared
349 * groupId which the algorithm is a member of.
350 *
351 * If this property is set to `false`, the DMAN3 library will fail
352 * to grant DMA channels to an algorithm requesting more TCCs or
353 * PaRams then the number configured for its scratch group.
354 *
355 * If this property is `true`, and an algorithm requests more TCCs or
356 * PaRams than the number configured for its scratch group, DMAN3 will
357 * do either of the following:
358 * @p(nlist)
359 * - If no algorithm is currently instantiated for the given scratch
360 * group, DMAN3 will bump up the number of TCCs and PaRams to the
361 * maximum of the number configured and that requested by the
362 * algorithm, for the scratch group. This will remain in effect
363 * until all algorithms for that scratch group are deleted.
364 * - If an algorithm has already been granted DMA channels for the
365 * given scratch group (so the number of TCCs and PaRams for that
366 * scratch group has already been determined by (1) above), and the
367 * number of TCCs or PaRams for the scratch group is insufficient for
368 * the algorithm currently requesting DMA channels, DMAN3 will
369 * allocate new TCCs and PaRams if available. These new TCCs and
370 * PaRams will not be shared by any other algorithm.
371 */
372 config bool allowUnshared = true;
373
374 }
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378