Server DSP image name |
bin/ti_platforms_evm3530/audio_copy.x64P |
BIOS-related Configuration |
defaultMemSegId | DDR2 |
enableLogging | true |
traceBufferSize | 0x00008000 |
logName | ti_sdo_ce_osal_LOG_Buffer |
logSize | 0x00000100 |
logType | circular |
logSeg | DDR2 |
|
Server Algorithms |
Codec name (alias) | auddec_copy |
Codec type | XDM audio decoder (ti.sdo.ce.audio.IAUDDEC) |
Package | ti.sdo.ce.examples.codecs.auddec_copy |
Module | AUDDEC_COPY |
Codec package location at server build time | /db/atree/library/trees/ce/ce-r09x/src/ |
Package version | [ 1, 0, 0 ] |
RPC protocol version |
3
|
Thread attributes |
Priority
|
2
|
Stack Size
|
default for the alg (1024 bytes) + 8192 bytes padding
|
|
Group ID number |
0 (auto-assigned value)
|
Codec name (alias) | audenc_copy |
Codec type | XDM audio encoder (ti.sdo.ce.audio.IAUDENC) |
Package | ti.sdo.ce.examples.codecs.audenc_copy |
Module | AUDENC_COPY |
Codec package location at server build time | /db/atree/library/trees/ce/ce-r09x/src/ |
Package version | [ 1, 0, 0 ] |
RPC protocol version |
3
|
Thread attributes |
Priority
|
2
|
Stack Size
|
default for the alg (1024 bytes) + 8192 bytes padding
|
|
Group ID number |
0 (auto-assigned value)
|
|
Server DMA (DMAN3) config |
MAXGROUPS | 0x00000014 |
heapInternal | L1DHEAP |
heapExternal | DDR2 |
scratchAllocFxn | undefined |
scratchFreeFxn | undefined |
idma3Internal | true |
cpu | false |
useExternalRM | false |
numQdmaChannels | 0x00000004 |
qdmaPaRamBase | 0x01C04000 |
maxPaRamEntries | 0x00000080 |
maxQdmaChannels | 0x00000008 |
maxTCs | 0x00000008 |
paRamBaseIndex | 0x00000060 |
numPaRamEntries | 0x00000020 |
nullPaRamIndex | 0x00000000 |
qdmaChannels | [ 0, 1, 2, 3 ] |
tccAllocationMaskH | 0xFFFFFFFF |
tccAllocationMaskL | 0x00000000 |
qdmaQueueMap | [ 1, 1, 1, 1, 1, 1, 1, 1 ] |
queueTCMap | [ 0, 1, 2, 3, 4, 5, 6, 7 ] |
queuePri | [ 3, 7, 0, 0, 0, 0, 0, 0 ] |
numTccGroup | [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] |
numPaRamGroup | [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] |
ipcKeyBase | 0x4E414D44 |
allowUnshared | true |
|
Algorithm memory allocation (DSKT2) config |
DEFAULTSEG | IRAM |
DARAM0 | DDRALGHEAP |
DARAM1 | DDRALGHEAP |
DARAM2 | DDRALGHEAP |
SARAM0 | DDRALGHEAP |
SARAM1 | DDRALGHEAP |
SARAM2 | DDRALGHEAP |
ESDATA | DDRALGHEAP |
IPROG | DDRALGHEAP |
EPROG | DDRALGHEAP |
DSKT2_HEAP | DDR2 |
ALLOW_EXTERNAL_SCRATCH | true |
DARAM_SCRATCH_SIZES | [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] |
SARAM_SCRATCH_SIZES | [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ] |
cacheWritebackInvalidateFxn | BCACHE_wbInv |
|
DSP memory map |
Name | MEM_NULL |
Base | 0x00000000 |
Len | 0x00000000 |
Description | Place holder segment which allows user to disable heaps |
Name | CACHE_L1D |
Base | 0x10F10000 |
Len | 0x00008000 |
Description | Do not delete, in use by cache |
Name | L4PER |
Base | 0x49000000 |
Len | 0x00100000 |
Description | L4PER: L4-Peripheral Interconnect Address Space |
Name | DDR2 |
Base | 0x87800000 |
Len | 0x00600000 |
Description | DDR2: off-chip memory for application code and data |
Name | IRAM |
Base | 0x107F8000 |
Len | 0x00008000 |
Description | Internal 96K L2 RAM/CACHE in UMAP0 |
Name | CACHE_L2 |
Base | 0x10800000 |
Len | 0x00010000 |
Description | Do not delete, in use by cache |
Name | L1DSRAM |
Base | 0x10F04000 |
Len | 0x0000C000 |
Description | Internal 80K RAM/CACHE L1 Data Memory in Region 0 |
Name | CACHE_L1P |
Base | 0x10E00000 |
Len | 0x00008000 |
Description | Do not delete, in use by cache |
Name | RESET_VECTOR |
Base | 0x87F00000 |
Len | 0x00001000 |
Description | RESET_VECTOR: off-chip memory for the reset vector table |
Name | DDRALGHEAP |
Base | 0x86000000 |
Len | 0x00001000 |
Description | DDRALGHEAP: off-chip memory for dynamic algmem allocation |
Name | L4CORE |
Base | 0x48000000 |
Len | 0x01000000 |
Description | L4CORE: L4-Core Interconnect Address Space |
Name | DSPLINKMEM |
Base | 0x87E00000 |
Len | 0x00100000 |
Description | DSPLINK: off-chip memory reserved for DSPLINK code and data |
Name | CMEM |
Base | <to be set to CMEM block address at server load time> |
Len | <to be set to CMEM block size at server load time> |
Description | placeholder for the CMEM segment that the Arm side creates for I/O buffer exchange with the DSP; on OMAP devices the CMEM segment is automatically mapped on the DSP at DSP server load time so the DSP can access the Arm I/O buffers |
|
Misc settings |
Server thread priority | 1 |
Server thread stack size | 2048 bytes |
autoGenScratchSizeArrays | true |
Skeleton Caching Policy | LOCALBUFFERINVWB (default) |
|
Configured DSP clock speed |
330 MHz (set in the GBL.CLKOUT TCF field; may or may not match the actual DSP clock speed) |
Configuration example |
Add the following code to your Arm-side application configuration file (.cfg) to create an Engine from this server:
var Engine = xdc.useModule('ti.sdo.ce.Engine');
var myEngine = Engine.createFromServer(
"bin/ti_platforms_evm3530/audio_copy", // Engine name (as referred to in the C app)
"bin/ti_platforms_evm3530/audio_copy.x64P", // path to server exe, relative to its package dir
"ti.sdo.ce.examples.servers.server_api_example" // full server package name
);
|