/*
 * arch/ppc/platform/tqm85xx_common.c
 *
 * MPC85xx TQM85xx board common routines
 *
 * Maintainer: Wolfgang Denk
 * Copyright 2005 DENX Software Engineering
 *
 * Copyright 2004 Freescale Semiconductor, Inc
 * Copyright 2002, 2003 Motorola Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/blk.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/seq_file.h>
#include <linux/serial.h>
#include <linux/module.h>

#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/atomic.h>
#include <asm/time.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/prom.h>
#include <asm/open_pic.h>
#include <asm/bootinfo.h>
#include <asm/pci-bridge.h>
#include <asm/mpc85xx.h>
#include <asm/irq.h>
#include <asm/immap_85xx.h>
#include <asm/ocp.h>

#include <mm/mmu_decl.h>

#include <platforms/tqm85xx_common.h>

#ifdef CONFIG_PCI
void tqm85xx_setup_hose(void);
#else
unsigned long isa_io_base = 0;
unsigned long isa_mem_base = 0;
#endif

extern unsigned long total_memory;	/* in mm/init */

unsigned char __res[sizeof (bd_t)];

/* Internal interrupts are all Level Sensitive, and Positive Polarity */

static u_char tqm85xx_openpic_initsenses[] __initdata = {
	(IRQ_POLARITY_POSITIVE),	/* Internal  0: L2 Cache */
	(IRQ_POLARITY_POSITIVE),	/* Internal  1: ECM */
	(IRQ_POLARITY_POSITIVE),	/* Internal  2: DDR DRAM */
	(IRQ_POLARITY_POSITIVE),	/* Internal  3: LBIU */
	(IRQ_POLARITY_POSITIVE),	/* Internal  4: DMA 0 */
	(IRQ_POLARITY_POSITIVE),	/* Internal  5: DMA 1 */
	(IRQ_POLARITY_POSITIVE),	/* Internal  6: DMA 2 */
	(IRQ_POLARITY_POSITIVE),	/* Internal  7: DMA 3 */
	(IRQ_POLARITY_POSITIVE),	/* Internal  8: PCI/PCI-X */
	(IRQ_POLARITY_POSITIVE),	/* Internal  9: RIO Inbound Port Write Error */
	(IRQ_POLARITY_POSITIVE),	/* Internal 10: RIO Doorbell Inbound */
	(IRQ_POLARITY_POSITIVE),	/* Internal 11: RIO Outbound Message */
	(IRQ_POLARITY_POSITIVE),	/* Internal 12: RIO Inbound Message */
	(IRQ_POLARITY_POSITIVE),	/* Internal 13: TSEC 0 Transmit */
	(IRQ_POLARITY_POSITIVE),	/* Internal 14: TSEC 0 Receive */
	(IRQ_POLARITY_POSITIVE),	/* Internal 15: Unused */
	(IRQ_POLARITY_POSITIVE),	/* Internal 16: Unused */
	(IRQ_POLARITY_POSITIVE),	/* Internal 17: Unused */
	(IRQ_POLARITY_POSITIVE),	/* Internal 18: TSEC 0 Receive/Transmit Error */
	(IRQ_POLARITY_POSITIVE),	/* Internal 19: TSEC 1 Transmit */
	(IRQ_POLARITY_POSITIVE),	/* Internal 20: TSEC 1 Receive */
	(IRQ_POLARITY_POSITIVE),	/* Internal 21: Unused */
	(IRQ_POLARITY_POSITIVE),	/* Internal 22: Unused */
	(IRQ_POLARITY_POSITIVE),	/* Internal 23: Unused */
	(IRQ_POLARITY_POSITIVE),	/* Internal 24: TSEC 1 Receive/Transmit Error */
	(IRQ_POLARITY_POSITIVE),	/* Internal 25: Fast Ethernet */
	(IRQ_POLARITY_POSITIVE),	/* Internal 26: DUART */
	(IRQ_POLARITY_POSITIVE),	/* Internal 27: I2C */
	(IRQ_POLARITY_POSITIVE),	/* Internal 28: Performance Monitor */
	(IRQ_POLARITY_POSITIVE),	/* Internal 29: Unused */
	(IRQ_POLARITY_POSITIVE),	/* Internal 30: CPM */
	(IRQ_POLARITY_POSITIVE),	/* Internal 31: Unused */
	0x0,				/* External  0: */
#if defined(CONFIG_PCI)
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 1: PCI slot 0 */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 2: PCI slot 1 */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 3: PCI slot 2 */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 4: PCI slot 3 */
#else
	0x0,				/* External  1: */
	0x0,				/* External  2: */
	0x0,				/* External  3: */
	0x0,				/* External  4: */
#endif
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 5: PHY */
	0x0,				/* External  6: */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 7: PHY */
	0x0,				/* External  8: */
	0x0,				/* External  9: */
	0x0,				/* External 10: */
	0x0,				/* External 11: */
};

/* ***********************************************************************
 *  The decrementer counts at the system (internal) clock frequency divided by 8
 */
void __init
tqm85xx_calibrate_decr(void)
{
	bd_t *binfo = (bd_t *) __res;
	unsigned int freq, divisor;

	/* get the core frequency */
	freq = binfo->bi_busfreq;
	/* The timebase is updated every 8 bus clocks, HID0[SEL_TBCLK] = 0 */
	divisor = 8;
	printk("time_init: decrementer frequency = %u.%.6u MHz\n",
	       freq / divisor / 1000000, (freq / divisor) % 1000000);
	tb_ticks_per_jiffy = freq / divisor / HZ;
	tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
}

/* *********************************************************************** */
unsigned long __init
tqm85xx_find_end_of_memory(void)
{
	bd_t *binfo;

	binfo = (bd_t *) __res;

	return binfo->bi_memsize;
}

/* ************************************************************************
 * tqm85xx doesn't have a mechanism to restart the system, It can
 * however reset itself
 */
void
tqm85xx_restart(char *cmd)
{
	local_irq_disable();
	abort();
}

/* ************************************************************************
 * tqm85xx has no support for this feature
 */
void
tqm85xx_power_off(void)
{
	local_irq_disable();
	for (;;) ;
}

/* ************************************************************************
 *  tqm85xx has support for this feature, but it hasn't been implemented
 */
void
tqm85xx_halt(void)
{
	local_irq_disable();
	for (;;) ;
}

/* ************************************************************************ */
int
tqm85xx_show_cpuinfo(struct seq_file *m)
{
	uint pvid, svid, phid1;
	uint memsize = total_memory;
	bd_t *binfo = (bd_t *) __res;
	unsigned int freq;

	/* get the bus frequency */
	freq = binfo->bi_busfreq;

	pvid = mfspr(PVR);
	svid = mfspr(SVR);

	seq_printf(m, "Vendor\t\t: Freescale\n");

	switch (svid & 0xffff0000) {
	case SVR_8540:
		seq_printf(m, "Machine\t\t: TQM8540\n");
		break;
	case SVR_8560:
		seq_printf(m, "Machine\t\t: TQM8560\n");
		break;
	default:
		seq_printf(m, "Machine\t\t: unknown\n");
		break;
	}
	seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000,
		   freq % 1000000);
	seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
	seq_printf(m, "SVR\t\t: 0x%x\n", svid);

	/* Display cpu Pll setting */
	phid1 = mfspr(HID1);
	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));

	/* Display the amount of memory */
	seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));

	return 0;
}

void __init
tqm85xx_init_IRQ(void)
{
	bd_t *binfo = (bd_t *) __res;
	/* Determine the Physical Address of the OpenPIC regs */
	phys_addr_t OpenPIC_PAddr =
	    binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
	OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
	OpenPIC_InitSenses = tqm85xx_openpic_initsenses;
	OpenPIC_NumInitSenses = sizeof (tqm85xx_openpic_initsenses);

	/* Skip reserved space and internal sources */
	openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
	/* Map PIC IRQs 0-11 */
	openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);

	/* we let openpic interrupts starting from an offset, to
	 * leave space for cascading interrupts underneath.
	 */
	openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);

	return;
}

#ifdef CONFIG_PCI
/*
 * interrupt routing
 */

static inline int
tqm85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
	static char pci_irq_table[][4] =
	    /*
	     * This is little evil, but works around the fact
	     * that revA boards have IDSEL starting at 18
	     * and others boards (older) start at 12
	     *
	     *      PCI IDSEL/INTPIN->INTLINE
	     *       A      B      C      D
	     */
	{
		{PIRQA, PIRQB, PIRQC, PIRQD},	/* IDSEL 2 */
		{PIRQD, PIRQA, PIRQB, PIRQC},
		{PIRQC, PIRQD, PIRQA, PIRQB},
		{PIRQB, PIRQC, PIRQD, PIRQA},	/* IDSEL 5 */
		{0, 0, 0, 0},	/* -- */
		{0, 0, 0, 0},	/* -- */
		{0, 0, 0, 0},	/* -- */
		{0, 0, 0, 0},	/* -- */
		{0, 0, 0, 0},	/* -- */
		{0, 0, 0, 0},	/* -- */
		{PIRQA, PIRQB, PIRQC, PIRQD},	/* IDSEL 12 */
		{PIRQD, PIRQA, PIRQB, PIRQC},
		{PIRQC, PIRQD, PIRQA, PIRQB},
		{PIRQB, PIRQC, PIRQD, PIRQA},	/* IDSEL 15 */
		{0, 0, 0, 0},	/* -- */
		{0, 0, 0, 0},	/* -- */
		{PIRQA, PIRQB, PIRQC, PIRQD},	/* IDSEL 18 */
		{PIRQD, PIRQA, PIRQB, PIRQC},
		{PIRQC, PIRQD, PIRQA, PIRQB},
		{PIRQB, PIRQC, PIRQD, PIRQA},	/* IDSEL 21 */
	};

	const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
	return PCI_IRQ_TABLE_LOOKUP;
}

static int
tqm85xx_exclude_device(u_char bus, u_char devfn)
{
	if (bus == 0 && PCI_SLOT(devfn) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;
	else
		return PCIBIOS_SUCCESSFUL;
}

void __init
tqm85xx_setup_pci(struct pci_controller *hose)
{
	volatile struct ccsr_pci *pci;
	volatile struct ccsr_guts *guts;
	unsigned short temps;
	bd_t *binfo = (bd_t *) __res;

	pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET,
		    MPC85xx_PCI1_SIZE);

	guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET,
		    MPC85xx_GUTS_SIZE);

	early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
	temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);

#define PORDEVSR_PCI	(0x00800000)	/* PCI Mode */
	if (guts->pordevsr & PORDEVSR_PCI) {
 		early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 	} else {
		/* PCI-X init */
		temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
			| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
		early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps);
	}

	/* Disable all windows (except powar0 since its ignored) */
	pci->powar1 = 0;
	pci->powar2 = 0;
	pci->powar3 = 0;
	pci->powar4 = 0;
	pci->piwar1 = 0;
	pci->piwar2 = 0;
	pci->piwar3 = 0;

	/* Setup 512M Phys:PCI 1:1 outbound mem window @ 0x80000000 */
	pci->potar1 = (TQM85XX_PCI_LOWER_MEM >> 12) & 0x000fffff;
	pci->potear1 = 0x00000000;
	pci->powbar1 = (TQM85XX_PCI_LOWER_MEM >> 12) & 0x000fffff;
	pci->powar1 = 0x8004401c;	/* Enable, Mem R/W, 512M */

	/* Setup 16M outboud IO windows @ 0xe2000000 */
	pci->potar2 = 0x00000000;
	pci->potear2 = 0x00000000;
	pci->powbar2 = (TQM85XX_PCI_IO_BASE >> 12) & 0x000fffff;
	pci->powar2 = 0x80088017;	/* Enable, IO R/W, 16M */

	/* Setup 2G inbound Memory Window @ 0 */
	pci->pitar1 = 0x00000000;
	pci->piwbar1 = 0x00000000;
	pci->piwar1 = 0xa0f5501e;	/* Enable, Prefetch, Local
					   Mem, Snoop R/W, 2G */
}

void __init
tqm85xx_setup_hose(void)
{
	struct pci_controller *hose;
	bd_t *binfo = (bd_t *) __res;

	hose = pcibios_alloc_controller();

	if (!hose)
		return;

	hose->first_busno = 0;
	hose->bus_offset = 0;
	hose->last_busno = 0xff;

	setup_indirect_pci(hose, binfo->bi_immr_base + PCI_CFG_ADDR_OFFSET,
			   binfo->bi_immr_base + PCI_CFG_DATA_OFFSET);
	hose->set_cfg_type = 1;

	tqm85xx_setup_pci(hose);

	hose->pci_mem_offset = TQM85XX_PCI_MEM_OFFSET;
	hose->mem_space.start = TQM85XX_PCI_LOWER_MEM;
	hose->mem_space.end = TQM85XX_PCI_UPPER_MEM;

	hose->io_space.start = TQM85XX_PCI_LOWER_IO;
	hose->io_space.end = TQM85XX_PCI_UPPER_IO;
	hose->io_base_phys = TQM85XX_PCI_IO_BASE;
	isa_io_base =
	    (unsigned long) ioremap(TQM85XX_PCI_IO_BASE,
				    TQM85XX_PCI_IO_SIZE);
	hose->io_base_virt = (void *) isa_io_base;

	/* setup resources */
	pci_init_resource(&hose->mem_resources[0],
			  TQM85XX_PCI_LOWER_MEM,
			  TQM85XX_PCI_UPPER_MEM,
			  IORESOURCE_MEM, "PCI host bridge");

	pci_init_resource(&hose->io_resource,
			  TQM85XX_PCI_LOWER_IO,
			  TQM85XX_PCI_UPPER_IO,
			  IORESOURCE_IO, "PCI host bridge");

	ppc_md.pci_exclude_device = tqm85xx_exclude_device;

	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);

	ppc_md.pci_swizzle = common_swizzle;
	ppc_md.pci_map_irq = tqm85xx_map_irq;

	return;
}
#endif /* CONFIG_PCI */
