/*
 * CPU86 board specific definitions
 * 
 * Copyright (c) 2004 Wolfgang Denk (wd@denx.de)
 */

#ifndef __MACH_CPU86_H
#define __MACH_CPU86_H

#include <linux/config.h>
 
#include <asm/ppcboot.h>

#define IMAP_ADDR		((uint)0xF0000000)

/*
 * CPU86 CS
 */
#define	CPU86_BOOT_CS		0	/* BootROM 		is on Chip Select 0	*/
#define CPU86_FLASH_CS		1	/* Flash	    is on Chip Select 1	*/
#define CPU86_SDRAM_CS		2	/* SDRAM	    is on Chip Select 2	*/
#define	CPU86_SRAM_CS		3	/* SRAM		    is on Chip Select 3	*/
#define CPU86_DOC_CS		4	/* DiskOnChip   is on Chip Select 4	*/
#define CPU86_FDC_CS		5	/* FDC37C78	    is on Chip Select 5	*/
#define CPU86_BCSR_CS		6	/* BCSR		    is on Chip Select 6	*/
#define CPU86_VME_EXT_CS	7	/* VME Extended I/O is on Chip Select 7	*/
#define CPU86_VME_STD_CS	8	/* VME Standard I/O is on Chip Select 8	*/
#define CPU86_VME_SHORT_CS	9	/* VME Short    I/O is on Chip Select 9	*/

/*
 * CPU86 local interrupts
 */
#define	CPU86_IRQ_ABORT		SIU_INT_IRQ1	/* Abort Key		*/
#define	CPU86_IRQ_SYSMON	SIU_INT_IRQ2	/* System Monitor	*/
#define CPU86_IRQ_VME_INTR	SIU_INT_IRQ3	/* VMEBus Interrupt	*/
#define	CPU86_IRQ_PMC		SIU_INT_IRQ4	/* PMC-IRQ (A,B,C,D)*/
#define	CPU86_IRQ_RTC		SIU_INT_IRQ5	/* RTC				*/
#define	CPU86_IRQ_FDC		SIU_INT_IRQ6	/* FDC37C78			*/
#define CPU86_IRQ_VMEF_MBOX	SIU_INT_IRQ7	/* Mailbox & SYSFAIL*/

/*
 * On the CPU86 here are 2 types of interrupts:
 *	  256 VME Bus Interrupts and
 *	  6 Onboard Interrupts (Abort Key, System Monitor, etc.)
 */
#define	NR_VME_INTERRUPTS	256

#define	CPU86_ONBOARD_IRQ_ABORT			(NR_VME_INTERRUPTS + 0)	
#define	CPU86_ONBOARD_IRQ_SYSMON		(NR_VME_INTERRUPTS + 1)
#define	CPU86_ONBOARD_IRQ_PMC			(NR_VME_INTERRUPTS + 2)
#define	CPU86_ONBOARD_IRQ_RTC			(NR_VME_INTERRUPTS + 3)
#define	CPU86_ONBOARD_IRQ_FDC			(NR_VME_INTERRUPTS + 4)
#define CPU86_ONBOARD_IRQ_VMEF_MBOX		(NR_VME_INTERRUPTS + 5)

/* Offset of the VMEbus Interrupt Acknowledge address range relative
 * to the start of the Short I/O address range.
 */
#define CPU86_VME_INTACK_OFFSET			0x80000

typedef volatile unsigned char	vuchar;

/*
 * CPU86 Board Control and Status registers
 */

typedef struct cpu86_bcsr_s {
	vuchar	vme_eacr;		/* VMEBus Extended Compare Register	*/
	vuchar	vme_sacr;		/* VMEBus Standard Compare Register	*/
	vuchar	vme_mbacr;		/* VMEBus Mailbox  Compare Register	*/
	vuchar	bd_ctrl;		/* Board Control Register			*/
	vuchar	bd_status;		/* Board Status Register			*/
	vuchar	wd_rport;		/* Watchdog Retrigger Port			*/
	vuchar	mbox_clear;		/* Clear Mailbox IRQ Port			*/
	vuchar	bd_rev;			/* Board Revision Register			*/
	vuchar	reserved[0x80 - 8];
	vuchar	vme_imask;		/* VMEBus Interrupt Mask Register	*/
	vuchar	vme_ipend;		/* VMEBus Interrupt Status Register	*/
	vuchar	onbd_imask;		/* Local Interrupt Mask Register	*/
	vuchar	onbd_ipend;		/* Local Interrupt Status Register	*/
	vuchar	pmc_ipend;		/* PMC Interrupt Status Register	*/
} cpu86_bcsr_t;

/*
 * Local Interrupt Mask Register bit map
 */
 
#define CPU86_ONBOARD_ABORT			0x01
#define CPU86_ONBOARD_MAILBOX		0x02
#define CPU86_ONBOARD_FDC			0x04
#define CPU86_ONBOARD_RTC			0x08
#define CPU86_ONBOARD_SYSMON		0x10
#define CPU86_ONBOARD_VME_SFAIL		0x20
#define CPU86_ONBOARD_PMC			0x40
#define CPU86_ONBOARD_VME_ACFAIL	0x80

#endif	/* __MACH_CPU86_H */
