/*
 * arch/ppc/platforms/4xx/ibm440gx.c
 *
 * PPC440GX I/O descriptions
 *
 * Matt Porter <mporter@mvista.com>
 * Copyright 2002-2003 MontaVista Software Inc.
 *
 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
 * Copyright (c) 2003 Zultys Technologies
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */
#include <linux/init.h>
#include <linux/module.h>
#include <platforms/ibm440gx.h>
#include <asm/ocp.h>

#if defined(EMAC_NUMS) && EMAC_NUMS > 0
u32 emac_phy_map[EMAC_NUMS];
EXPORT_SYMBOL(emac_phy_map);
#endif

struct ocp_func_emac_data ibm440gx_emac0_def = {
	.rgmii_idx	= -1,		/* No RGMII */
	.rgmii_mux	= -1,		/* No RGMII */
	.zmii_idx       = 0,            /* ZMII device index */
	.zmii_mux       = 0,            /* ZMII input of this EMAC */
	.mal_idx        = 0,            /* MAL device index */
	.mal_rx_chan    = 0,            /* MAL rx channel number */
	.mal_tx_chan   	= 0,            /* MAL tx channel 1 number */
	.wol_irq        = BL_MAC_WOL,   /* WOL interrupt number */
	.mdio_idx       = -1,           /* No shared MDIO */
	.tah_idx	= -1,		/* No TAH */
};
EXPORT_SYMBOL(ibm440gx_emac0_def);

struct ocp_func_emac_data ibm440gx_emac1_def = {
	.rgmii_idx	= -1,		/* No RGMII */
	.rgmii_mux	= -1,		/* No RGMII */
	.zmii_idx       = 0,            /* ZMII device index */
	.zmii_mux       = 1,            /* ZMII input of this EMAC */
	.mal_idx        = 0,            /* MAL device index */
	.mal_rx_chan    = 1,            /* MAL rx channel number */
	.mal_tx_chan  	= 1,            /* MAL tx channel 1 number */
	.wol_irq        = BL_MAC_WOL1,  /* WOL interrupt number */
	.mdio_idx       = -1,           /* No shared MDIO */
	.tah_idx	= -1,	/* No TAH */
};
EXPORT_SYMBOL(ibm440gx_emac1_def);

struct ocp_func_emac_data ibm440gx_emac2_def = {
	.rgmii_idx	= 0,		/* RGMII device index */
	.rgmii_mux	= 0,		/* RGMII input of this EMAC */
	.zmii_idx       = 0,            /* ZMII device index */
	.zmii_mux       = 2,            /* ZMII input of this EMAC */
	.mal_idx        = 0,            /* MAL device index */
	.mal_rx_chan    = 2,            /* MAL rx channel number */
	.mal_tx_chan 	= 2,            /* MAL tx channel 1 number */
	.wol_irq        = 65,           /* WOL interrupt number */
	.mdio_idx       = -1,           /* No shared MDIO */
	.tah_idx	= 0,		/* TAH device index */
	.jumbo		= 1,		/* Jumbo frames supported */
};
EXPORT_SYMBOL(ibm440gx_emac2_def);

struct ocp_func_emac_data ibm440gx_emac3_def = {
	.rgmii_idx	= 0,		/* RGMII device index */
	.rgmii_mux	= 1,		/* RGMII input of this EMAC */
	.zmii_idx       = 0,            /* ZMII device index */
	.zmii_mux       = 3,            /* ZMII input of this EMAC */
	.mal_idx        = 0,            /* MAL device index */
	.mal_rx_chan    = 3,            /* MAL rx channel number */
	.mal_tx_chan    = 3,            /* MAL tx channel 1 number */
	.wol_irq        = 67,           /* WOL interrupt number */
	.mdio_idx       = -1,           /* No shared MDIO */
	.tah_idx	= 1,		/* TAH device index */
	.jumbo		= 1,		/* Jumbo frames supported */
};
EXPORT_SYMBOL(ibm440gx_emac3_def);

static struct ocp_func_mal_data ibm440gx_mal0_def = {
	.num_tx_chans   = 2*EMAC_NUMS,  /* Number of TX channels */
	.num_rx_chans   = EMAC_NUMS,    /* Number of RX channels */
};

struct ocp_def core_ocp[] __initdata = {
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_OPB,
	  .index	= 0,
	  .paddr	= PPC440GX_OPB_BASE_START,
	  .irq		= OCP_IRQ_NA,
	  .pm		= OCP_CPM_NA,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_16550,
	  .index	= 0,
	  .paddr	= PPC440GX_UART0_ADDR,
	  .irq		= UART0_INT,
	  .pm		= IBM_CPM_UART0,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_16550,
	  .index	= 1,
	  .paddr	= PPC440GX_UART1_ADDR,
	  .irq		= UART1_INT,
	  .pm		= IBM_CPM_UART1,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_IIC,
	  .index	= 0,
	  .paddr	= PPC440GX_IIC0_ADDR,
	  .irq		= IIC0_IRQ,
	  .pm		= IBM_CPM_IIC0,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_IIC,
	  .index	= 1,
	  .paddr	= PPC440GX_IIC1_ADDR,
	  .irq		= IIC1_IRQ,
	  .pm		= IBM_CPM_IIC1,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_GPIO,
	  .index	= 0,
	  .paddr	= PPC440GX_GPIO0_ADDR,
	  .irq		= OCP_IRQ_NA,
	  .pm		= IBM_CPM_GPIO0,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_MAL,
	  .paddr	= OCP_PADDR_NA,
	  .irq		= OCP_IRQ_NA,
	  .pm		= OCP_CPM_NA,
	  .additions	= &ibm440gx_mal0_def,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_EMAC,
	  .index	= 0,
	  .paddr	= PPC440GX_EMAC0_ADDR,
	  .irq		= BL_MAC_ETH0,
	  .pm		= OCP_CPM_NA,
	  .additions	= &ibm440gx_emac0_def,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_EMAC,
	  .index	= 1,
	  .paddr	= PPC440GX_EMAC1_ADDR,
	  .irq		= BL_MAC_ETH1,
	  .pm		= OCP_CPM_NA,
	  .additions	= &ibm440gx_emac1_def,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_EMAC,
	  .index	= 2,
	  .paddr	= PPC440GX_EMAC2_ADDR,
	  .irq		= BL_MAC_ETH2,
	  .pm		= OCP_CPM_NA,
	  .additions	= &ibm440gx_emac2_def,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_EMAC,
	  .index	= 3,
	  .paddr	= PPC440GX_EMAC3_ADDR,
	  .irq		= BL_MAC_ETH3,
	  .pm		= OCP_CPM_NA,
	  .additions 	= &ibm440gx_emac3_def,
	},
    { .vendor   = OCP_VENDOR_IBM,
      .function = OCP_FUNC_RGMII,
      .paddr    = 0x0000000140000790ULL,
      .irq		= OCP_IRQ_NA,
      .pm		= OCP_CPM_NA,
    },
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_ZMII,
	  .paddr	= PPC440GX_ZMII_ADDR,
	  .irq		= OCP_IRQ_NA,
	  .pm		= OCP_CPM_NA,
	},
  	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_TAH,
	  .index	= 0,
	  .paddr	= 0x0000000140000b50ULL,
	  .irq		= 68,
	  .pm		= OCP_CPM_NA,
	},
	{ .vendor	= OCP_VENDOR_IBM,
	  .function	= OCP_FUNC_TAH,
	  .index	= 1,
	  .paddr	= 0x0000000140000d50ULL,
	  .irq		= 69,
	  .pm		= OCP_CPM_NA,
	},
	{ .vendor	= OCP_VENDOR_INVALID
	}
};
