/*
 * arch/ppc/platforms/alaska.h
 *
 * Definitions for Motorola Alaska MPC8220 Standard Development Platform
 * Board Support Package. Based on MGT5100.
 *
 * Alaska FPGA registers definitions by pbarada.
 *
 * Modification of Dale Farnsworth's <dale.farnsworth@mvista.com>
 * version made by Kent Borg.
 *
 * Copyright 2003 Motorola Inc.
 * Copyright 2001, 2004 MontaVista Software Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * From Processor to PCI:
 *   PCI Mem Space: 0x80000000 - 0xa0000000 -> 0x80000000 - 0xa0000000 (512 MB)
 *   PCI I/O Space: 0xfe400000 - 0xfeef0000 -> 0x00000000 - 0x00b00000 (11 MB)
 *      Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
 *
 * From PCI to Processor:
 *   System Memory: 0x00000000 -> 0x00000000
 */

#ifndef __PLATFORMS_ALASKA_H
#define __PLATFORMS_ALASKA_H

#include <linux/config.h>
#include <asm/mpc8220.h>

#define CRYSTAL_HZ		60000000

/* CPLD registers (8-bit) */
#define CPLD_CFG1		0xf1000000
#define CPLD_CFG1_REV_MASK	0x7
#define CPLD_CFG1_REV_SHIFT	5
#define CPLD_CFG1_REV_GET(x)	(((x) >> CPLD_CFG1_REV_SHIFT) & CPLD_CFG1_REV_MASK)
#define CPLD_CFG1_CF3		0x10
#define CPLD_CFG1_CF2		0x08
#define CPLD_CFG1_CF1		0x04
#define CPLD_CFG1_CF0		0x02
#define CPLD_CFG1_BOOT		0x01
#define CPLD_CFG1_SWITCHES	(CPLD_CFG1_CF3|CPLD_CFG1_CF2|CPLD_CFG1_CF1|CPLD_CFG1_CF0|CPLD_CFG1_BOOT)

#define CPLD_CTRL		0xf1000001
#define	CPLD_CTRL_SFTRST	0x80 /* setting this bit resets the board */
#define CPLD_CTRL_DEBUG		0x10
#define CPLD_CTRL_BOOT_WP	0x08
#define CPLD_CTRL_FLASH_WP	0x04
#define CPLD_CTRL_LED2		0x02
#define CPLD_CTRL_LED1		0x01

#define CPLD_PHY		0xf1000003
#define CPLD_PHY_EPHY_LINK	0x80
#define CPLD_PHY_100MB		0x40
#define CPLD_PHY_STATUS		0x10
#define CPLD_PHY_STATUS_1284	0x10
#define CPLD_PHY_STATUS_FEC1	0x00
#define CPLD_PHY_SELECT		0x08
#define CPLD_PHY_SELECT_1284	0x08
#define CPLD_PHY_SELECT_PHY1	0x00
#define CPLD_PHY_MANUAL		0x04
#define CPLD_PHY_MANUAL_AMBER	0x02
#define CPLD_PHY_MANUAL_GREEN	0x01

/* FPGA registers (32-bit access is the only allowed) */
#define FPGA_START		0xf2000000
#define FPGA_CTRL2		0xf2000004
#define FPGA_CTRL2_PEV_SEL	0x80
#define FPGA_CTRL2_DEV_SEL	0x40
#define FPGA_CTRL2_FP_SEL	0x20
#define FPGA_CTRL2_DEV_LOOP	0x10
#define FPGA_CTRL2_VFIFO_RESET	0x04
#define FPGA_CTRL2_FP_RESET	0x02
#define FPGA_CTRL2_FPGA_RESET	0x01

#define FPGA_USB_CONTROL	0xf2000008
#define FPGA_INT_ENABLE		0xf2000010
#define FPGA_INT_STATUS		0xf2000014

#define ALASKA_FPGA_INT_BASE	(MPC8220_PERP_IRQ_BASE + MPC8220_PERP_IRQ_NUM)
#define ALASKA_FPGA_INT_HIGHEST		(21 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__LED		(21 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__HSYNCH		(20 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__END_PAGE	(19 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__PHY2		(18 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__PHY1		(17 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__USB		(16 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__SERIAL2	(15 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__SERIAL1	(14 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__CONSOLE	(13 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__ENG_STS	(12 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__PCI4		( 8 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__PCI3		( 9 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__PCI2		(10 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__PCI1		(11 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__VFIFO_FF	( 7 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__VFIFO_AF	( 6 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__VFIFO_AE	( 5 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT__VFIFO_EE	( 4 + ALASKA_FPGA_INT_BASE)
#define ALASKA_FPGA_INT_LOWEST		( 4 + ALASKA_FPGA_INT_BASE)

#define ALASKA_FPGA_IRQ		(MPC8220_IRQ1)

void alaska_init_irq(void);
int alaska_get_irq(struct pt_regs *regs);

/* Debug Card registers (8-bit) */
#define DEBUG_CARD_STATUS			0xf1001001 /* reading */
#define DEBUG_CARD_STATUS_PADDLEBOARD_MODE	0x00
#define DEBUG_CARD_STATUS_WAVEMARK_DEBUG_MODE	0x08

#define DEBUG_CARD_CONTROL			0xf1001001 /* writing */
#define DEBUG_CARD_CONTROL_DP0			0x04
#define DEBUG_CARD_CONTROL_DP1			0x02

#define DEBUG_CARD_SWITCH			0xf1001002 /* reading */
#define DEBUG_CARD_HEXLED			0xf1001002 /* writing */

#define DEBUG_CARD_SCRATCH0			0xf100100f
#define DEBUG_CARD_SCRATCH1			0xf1001017

/* PCI */
#define ALASKA_PCI_CONFIG_ADDR			0xfe000cf8
#define ALASKA_PCI_CONFIG_DATA			0xfe000cfc

#define ALASKA_PROC_PCI_IO_START		0xfe400000U
#define ALASKA_PROC_PCI_IO_END			0xfeefffffU

#define ALASKA_PROC_PCI_MEM_START		0x80000000U
#define ALASKA_PROC_PCI_MEM_END 		0x9fffffffU

#define ALASKA_PCI_DRAM_OFFSET			0x00000000U
#define ALASKA_PCI_PHY_MEM_OFFSET		0x00000000U

#define ALASKA_ISA_IO_BASE			(ALASKA_PROC_PCI_IO_START)
#define ALASKA_ISA_MEM_BASE			0x00000000U

/* Serial port definitions */

#define RS_TABLE_SIZE				1

/* Flash definitions */
#define FLASH_ADDR 0xfe000000
#define FLASH_SIZE 0x00f00000

/* this is the peripheral bus speed */
/* XXXXX
#define BASE_BAUD				120000000L

#define STD_PSC_OP						\
{								\
	.magic		= 0,					\
	.baud_base	= BASE_BAUD,				\
	.irq		= MPC8220_PSC_IRQ,			\
	.flags		= ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST,	\
	.iomem_base	= (void *)MPC8220_PSC,			\
	.io_type	= SERIAL_IO_MEM,			\
},
#define SERIAL_PORT_DFNS			STD_PSC_OP
*/

#ifdef CONFIG_MGT_PSC
/*
 * The Icecube uses PSC1 as the console
 */
#define ALASKA_CONSOLE_PSC                              (MGT_PSC1)

#define RS_TABLE_SIZE                                   1

/* this is the peripheral bus speed */
#define BASE_BAUD                                               60000000L

#define STD_PSC_OP(num)                                                                                                 \
{                                                                                                                                               \
	magic:          0,                                                                                                              \
	baud_base:      BASE_BAUD,                                                                                              \
	irq:            MGT_PSC##num##_IRQ,                                                                             \
	flags:          ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST,                                    \
	iomem_base:     (void *)MGT_PSC##num##,                                                                 \
	io_type:        SERIAL_IO_MEM,                                                                                  \
},                                                                                                                                              \
#define SERIAL_PORT_DFNS                                STD_PSC_OP(1)

#else /* CONFIG_MGT_PSC */

#define RS_TABLE_SIZE                                   2

/* not 18432000L? */
#define BASE_BAUD                                               1152000L

#define SERIAL_PORT_DFNS                                                                                                \
{                                                                                                                                               \
	magic:          0,                                                                      \
	baud_base:      BASE_BAUD,                                                              \
	irq:            ALASKA_FPGA_INT__SERIAL1,                                                               \
	flags:          ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST,                                    \
	iomem_base:     (unsigned char*)(0xF1000000+0x1000+0x8),                                \
	iomem_reg_shift:0,                                                                      \
	io_type:        SERIAL_IO_MEM,                                                                                  \
},                                                                                              \
{                                                                                               \
	magic:          0,                                                                      \
	baud_base:      BASE_BAUD,                                                              \
	irq:            ALASKA_FPGA_INT__SERIAL2,                                                               \
	flags:          ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST,                                    \
	iomem_base:     (unsigned char*)(0xF1000000+0x1000+0x10),                               \
	iomem_reg_shift:0,                                                                      \
	io_type:        SERIAL_IO_MEM,                                                          \
},

#endif /* CONFIG_MGT_PSC */


/* Keep all the boot settings in one place: */

#define BOOTSIGNATURE				0xb8c3ba11

typedef struct _BootParams
{
	u32 MemSize;		/* Total DRAM size in bytes */
	u32 XLBClock;		/* XLB clock in Hz */
	u32 InputClock;		/* input clock in Hz */
	u32 CoreClock;		/* core clock in Hz */
	u32 VCOClock;		/* VCO clock in Hz */
	u32 FlexClock;		/* Flexbus clock in Hz */
	u32 signature;		/* magic number */
	u8 *version;		/* pointer to bootROM version string */
	u8 *buildDate;		/* pointer to bootROM buildDate string */
} BootParams;

/* Where the boot code stashes this information */
#define BOOTPARAMS_ADDRESS			(MPC8220_SRAM_START)

#endif /* __PLATFORMS_ALASKA_H */
